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MPC8343VRAGDB Datasheet(PDF) 5 Page - Freescale Semiconductor, Inc |
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MPC8343VRAGDB Datasheet(HTML) 5 Page - Freescale Semiconductor, Inc |
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5 / 79 page  MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 10 Freescale Semiconductor 5 Overview — Can operate as a stand-alone USB host controller – USB root hub with one downstream-facing port – Enhanced host controller interface (EHCI) compatible – High-speed (480 Mbps), full-speed (12 Mbps), and low-speed (1.5 Mbps) operations — External PHY with UTMI, serial and UTMI+ low-pin interface (ULPI) • Local bus controller (LBC) — Multiplexed 32-bit address and data operating at up to 133 MHz — Eight chip selects for eight external slaves — Up to eight-beat burst transfers — 32-, 16-, and 8-bit port sizes controlled by an on-chip memory controller — Three protocol engines on a per chip select basis: – General-purpose chip select machine (GPCM) – Three user-programmable machines (UPMs) – Dedicated single data rate SDRAM controller — Parity support — Default boot ROM chip select with configurable bus width (8-, 16-, or 32-bit) • Programmable interrupt controller (PIC) — Functional and programming compatibility with the MPC8260 interrupt controller — Support for 8 external and 35 internal discrete interrupt sources — Support for 1 external (optional) and 7 internal machine checkstop interrupt sources — Programmable highest priority request — Four groups of interrupts with programmable priority — External and internal interrupts directed to host processor — Redirects interrupts to external INTA pin in core disable mode. — Unique vector number for each interrupt source • Dual industry-standard I2C interfaces — Two-wire interface — Multiple master support — Master or slave I2C mode support — On-chip digital filtering rejects spikes on the bus — System initialization data optionally loaded from I2C-1 EPROM by boot sequencer embedded hardware • DMA controller — Four independent virtual channels — Concurrent execution across multiple channels with programmable bandwidth control — Handshaking (external control) signals for all channels: DMA_DREQ[0:3], DMA_DACK[0:3], DMA_DDONE[0:3] — All channels accessible to local core and remote PCI masters |
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