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MCM69R818CZP6 Datasheet(PDF) 6 Page - Motorola, Inc |
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MCM69R818CZP6 Datasheet(HTML) 6 Page - Motorola, Inc |
6 / 20 page MCM69R736C •MCM69R818C 6 MOTOROLA FAST SRAM DC OPERATING CONDITIONS AND CHARACTERISTICS (VDD = 3.3 V + 10%, – 5%, 0°C ≤ TA ≤ 70°C, Unless Otherwise Noted) RECOMMENDED OPERATING CONDITIONS (See Notes 1 through 4) Parameter Symbol Min Max –4 Max –4.4 Max –5 Max –6 Max Unit Notes Core Power Supply Voltage VDD 3.15 — — — — 3.6 V Output Driver Supply Voltage VDDQ 1.4 — — — — 1.9 V Active Power Supply Current (Device Selected, All Outputs Open, Freq = Max, VDD = Max, VDDQ = Max). Includes Supply Currents for VDD. IDD1 — 795 775 750 750 — mA 5 Quiescent Active Power Supply Current (Device Selected, All Outputs Open, Freq = 0, VDD = Max, VDDQ = Max). Includes supply currents for VDD. IDD2 — 540 540 540 540 — mA 6 Active Standby Power Supply Current (Device Deselected, Freq = Max, VDD = Max, VDDQ = Max) ISB1 — 400 400 400 400 — mA 7 CMOS Standby Supply Current (Device Deselected, Freq = 0, VDD = Max, VDDQ = Max, All Inputs Static at CMOS Levels) ISB2 — 390 390 390 390 — mA 6, 7 Sleep Mode Current (ZZ = VIH, Freq = Max, VDD = Max, VDDQ = Max) IZZ — 100 100 100 100 — mA 6 Input Reference DC Voltage Vref (dc) 0.6 — — — — 1.1 V 8 NOTES: 1. All data sheet parameters specified to full range of VDD unless otherwise noted. All voltages are referenced to voltage applied to VSS bumps. 2. Supply voltage applied to VDD connections. 3. Supply voltage applied to VDDQ connections. 4. All power supply currents measured with outputs open or deselected. 5. 50% read and 50% write; all addresses switching. 6. CMOS levels for I/Os are VIC ≤ VSS + 0.2 V or ≥ VDDQ – 0.2 V. CMOS levels for other inputs are Vin ≤ VSS + 0.2 V or ≥ VDD – 0.2 V. 7. Device deselected as defined by the Truth Table. 8. Although considerable latitude in the selection of the nominal dc value (i.e., rms value) of Vref is supported, the peak–to–peak ac compo- nent superimposed on Vref may not exceed 5% of the dc component of Vref. DC INPUT CHARACTERISTICS Parameter Symbol Min Max Unit Notes DC Input Logic High VIH (dc) Vref + 0.1 VDD + 0.3 V DC Input Logic Low VIL (dc) –0.3 Vref – 0.1 V 1 Input Leakage Current Ilkg(I) — ±5 µA 2 Clock Input Signal Voltage Vin (dc) –0.3 VDD + 0.3 V Clock Input Differential Voltage (See Figure 3) VDIF (dc) 0.2 VDD + 0.6 V 3 Clock Input Common Mode Voltage Range (See Figure 3) VCM (dc) 0.6 1.1 V 4 NOTES: 1. Inputs may undershoot to –1.5 V (peak) for up to 35% tKHKH (e.g., 1.5 ns at a clock cycle time of 4.4 ns). See FIgure 2. 2. 0 V ≤ Vin ≤ VDD for all pins. 3. Minimum instantaneous differential input voltage required for differential input clock operation. 4. Maximum rejectable common mode input voltage variation. Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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