MCM69R736C

•MCM69R818C

9

MOTOROLA FAST SRAM

Parameter

Symbol

Min

Max

Notes

AC Input Logic High (See Figure 4)

VIH (ac)

Vref + 200 mV

—

AC Input Logic Low (See Figures 2 and 4)

VIL (ac)

—

Vref – 200 mV

2

Input Reference Peak–to–Peak AC Voltage

Vref (ac)

—

5% Vref (dc)

3

Clock Input Differential Voltage

Vdif (ac)

400 mV

VDDQ + 600 mV

4

NOTES:

1. Inputs may overshoot to VDD + 1.5 V (peak) for up to 35% tKHKH (e.g., 1.5 ns at a clock cycle time of 4.4 ns). See Figure 2.

2. Inputs may undershoot to –0.5 V (peak) for up to 20% tKHKH (e.g., 2 ns at a clock cycle time of 10 ns). See Figure 2.

3. Although considerable latitude in the selection of the nominal dc value (i.e., rms value) of Vref is supported, the peak–to–peak ac compo-

nent superimposed on Vref may not exceed 5% of the dc component of Vref.

4. Minimum instantaneous differential input voltage required for differential input clock operation.

VIH

VSS

–1.0 V

–1.5 V

35% tKHKH

Figure 2. Undershoot Voltage

CROSSING POINT

VDDQ

VSS

VTR

VDIF

VCP

VCM*

Figure 3. Differential Inputs/Common Mode Input Voltage

*VCM, the Common Mode Input Voltage, equals VTR – [(VTR – VCP)/2].

VIH(ac)

Vref

VIL(ac)

VDDQ

VSS

Figure 4. AC Input Conditions

Freescale Semiconductor, Inc.

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