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MCM69R736CZP4R Datasheet(PDF) 8 Page - Motorola, Inc |
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MCM69R736CZP4R Datasheet(HTML) 8 Page - Motorola, Inc |
8 / 20 page MCM69R736C •MCM69R818C 8 MOTOROLA FAST SRAM AC OPERATING CONDITIONS AND CHARACTERISTICS (VDD = 3.3 V + 10%, – 5%, 0°C ≤ TA ≤ 70°C, Unless Otherwise Noted) Input Pulse Levels 0.25 to 1.25 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Rise/Fall Time 1 V/ns (20% to 80%) . . . . . . . . . . . . . . . . . . . . . . Input Timing Measurement Reference Level 0.75 V . . . . . . . . . . . . . . Output Timing Reference Level 0.75 V . . . . . . . . . . . . . . . . . . . . . . . . . Clock Input Timing Reference Level Differential Cross–Point . . . . . . ZQ for 50 Ω Impedance 250 Ω . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . R θJA Device 22 _C/W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . READ/WRITE CYCLE TIMING 69R736C–4 69R818C–4 69R736C–4.4 69R818C–4.4 69R736C–5 69R818C–5 69R736C–6 69R818C–6 Parameter Symbol Min Max Min Max Min Max Min Max Unit Notes Cycle Time tKHKH 4 — 4.4 — 5 — 6 — ns Clock High Pulse Width tKHKL 1.5 — 1.5 — 2 — 2.4 — ns Clock Low Pulse Width tKLKH 1.5 — 1.5 — 2 — 2.4 — ns Clock High to Output Low–Z tKHQX1 0.5 — 1 — 1 — 1 — ns 1, 2 Clock High to Output Valid tKHQV — 2 — 2.2 — 2.5 — 3 ns Clock High to Output Hold tKHQX 0.7 — 0.7 — 1 — 1 — ns 1 Clock High to Output High–Z tKHQZ — 2 — 2.2 — 2.5 — 3 ns 1, 2 Output Enable Low to Output Low–Z tGLQX 0.5 — 0.5 — 0.5 — 0.5 — ns Output Enable Low to Output Valid tGLQV — 2 — 2.2 — 2.5 — 3 ns Output Enable to Output Hold tGHQX 0.5 — 0.5 — 0.5 — 0.5 — ns Output Enable High to Output High–Z tGHQZ — 2 — 2.2 — 2.5 — 3 ns 1, 2 ZZ High to Sleep Mode tZZE — 50 — 50 — 50 — 50 ns ZZ Low to Recovery tZZR 200 — 200 — 200 — 200 — ns Setup Times: Address Data In Chip Select Write Enable tAVKH tDVKH tSVKH tWVKH 0.5 — 0.5 — 0.5 — 0.5 — ns Hold Times: Address Data In Chip Select Write Enable tKHAX tKHDX tKHSX tKHWX 0.75 — 0.75 — 1 — 1 — ns NOTES: 1. This parameter is sampled and not 100% tested. 2. Measured at ±200 mV from steady state. 3. Guaranteed by design only. The table of timing values shows either a mini- mum or a maximum limit for each parameter. Input requirements are specified from the external system point of view. Thus, address setup time is shown as a minimum since the system must supply at least that much time. On the other hand, responses from the memory are specified from the device point of view. Thus, the access time is shown as a maximum since the device never provides data later than that time. TIMING LIMITS DEVICE UNDER TEST ZQ 50 Ω 50 Ω 0.75 V VDDQ/2 Vref 250 Ω Figure 1. AC Test Load Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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