MCM63F737K

•MCM63F819K

4

MOTOROLA FAST SRAM

MCM63F737K TQFP PIN DESCRIPTIONS

Pin Locations

Symbol

Type

Description

85

ADSC

Input

Synchronous Address Status Controller: Active low, interrupts any

ongoing burst and latches a new external address. Used to initiate a

READ, WRITE, or chip deselect.

84

ADSP

Input

Synchronous Address Status Processor: Active low, interrupts any

ongoing burst and latches a new external address. Used to initiate a

new READ, WRITE, or chip deselect (exception — chip deselect does

not occur when ADSP is asserted and SE1 is high).

83

ADV

Input

Synchronous Address Advance: Increments address count in

accordance with counter type selected (linear/interleaved).

(a) 51, 52, 53, 56, 57, 58, 59, 62, 63

(b) 68, 69, 72, 73, 74, 75, 78, 79, 80

(c) 1, 2, 3, 6, 7, 8, 9, 12, 13

(d) 18, 19, 22, 23, 24, 25, 28, 29, 30

DQx

I/O

Synchronous Data I/O: “x” refers to the byte being read or written

(byte a, b, c, d).

86

G

Input

Asynchronous Output Enable Input:

Low — enables output buffers (DQx pins).

High — DQx pins are high impedance.

89

K

Input

Clock: This signal registers the address, data in, and all control signals

except G, LBO, and ZZ.

31

LBO

Input

Linear Burst Order Input: This pin must remain in steady state (this

signal not registered or latched). It must be tied high or low.

Low — linear burst counter.

High — interleaved burst counter.

32, 33, 34, 35, 44, 45, 46, 47, 48, 49, 50,

81, 82, 99, 100

SA

Input

Synchronous Address Inputs: These inputs are registered and must

meet setup and hold times.

36, 37

SA1, SA0

Input

Synchronous Address Inputs: These pins must be wired to the two

LSBs of the address bus for proper burst operation. These inputs are

registered and must meet setup and hold times.

93, 94, 95, 96

(a) (b) (c) (d)

SBx

Input

Synchronous Byte Write Inputs: “x” refers to the byte being written

(byte a, b, c, d). SGW overrides SBx.

98

SE1

Input

Synchronous Chip Enable: Active low to enable chip.

Negated high — blocks ADSP or deselects chip when ADSC is

asserted.

97

SE2

Input

Synchronous Chip Enable: Active high for depth expansion.

92

SE3

Input

Synchronous Chip Enable: Active low for depth expansion.

88

SGW

Input

Synchronous Global Write: This signal writes all bytes regardless of the

status of the SBx and SW signals. If only byte write signals SBx are

being used, tie this pin high.

87

SW

Input

Synchronous Write: This signal writes only those bytes that have been

selected using the byte write SBx pins. If only byte write signals SBx

are being used, tie this pin low.

64

ZZ

Input

Sleep Mode: This active high asynchronous signal places the RAM into

the lowest power mode. The ZZ pin disables the RAMs internal clock

when placed in this mode. When ZZ is negated, the RAM remains in

low power mode until it is commanded to READ or WRITE. Data

integrity is maintained upon returning to normal operation.

15, 41, 65, 91

VDD

Supply

Core Power Supply.

4, 11, 20, 27, 54, 61, 70, 77

VDDQ

Supply

I/O Power Supply.

5, 10, 17, 21, 26, 40, 55, 60, 67, 71,

76, 90

VSS

Supply

Ground.

14, 16, 38, 39, 42, 43, 66

NC

—

No Connection: There is no connection to the chip.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com