MCM63F837

•MCM63F919

11

MOTOROLA FAST SRAM

DC OPERATING CONDITIONS AND CHARACTERISTICS

(VDD = 3.3 V ±5%, TA = 0 to 70°C, Unless Otherwise Noted)

Parameter

Symbol

Min

Typ

Max

Unit

2.5 V I/O SUPPLY

Supply Voltage

VDD

3.135

3.3

3.465

V

I/O Supply Voltage

VDDQ

2.375

2.5

2.9

V

Input Low Voltage

VIL

–0.3*

—

0.7

V

Input High Voltage

VIH

1.7

—

VDD + 0.3**

V

Input High Voltage I/O Pins

VIH2

1.7

—

VDDQ + 0.3**

V

Output Low Voltage (IOL = 2 mA)

VOL

—

—

0.7

V

Output High Voltage (IOH = –2 mA)

VOH

1.7

—

—

V

3.3 V I/O SUPPLY

Supply Voltage

VDD

3.135

3.3

3.465

V

I/O Supply Voltage

VDDQ

3.135

3.3

VDD

V

Input Low Voltage

VIL

–0.5*

—

0.8

V

Input High Voltage

VIH

2

—

VDD + 0.5**

V

Input High Voltage I/O Pins

VIH2

2

—

VDDQ + 0.5**

V

Output Low Voltage (IOL = 8 mA)

VOL

—

—

0.4

V

Output High Voltage (IOH = –4 mA)

VOH

2.4

—

—

V

* Undershoot: VIL ≤ – 1.5 V for t < 20% tKHKH.

** Overshoot: VIH/VIH2 ≤ VDD/VDDQ + 1.0 V (not to exceed 4.6 V) for t < 20% tKHKH.

SUPPLY CURRENTS

Parameter

Symbol

Min

Typ

Max

Unit

Notes

Input Leakage Current (0 V

≤ Vin ≤ VDD)

Ilkg(I)

—

—

±1

µA

1

Output Leakage Current (0 V

≤ Vin ≤ VDDQ)

Ilkg(O)

—

—

±1

µA

AC Supply Current (Device Selected,

MCM63F837/919–7

All Outputs Open, Freq = Max)

MCM63F837/919–8

Includes VDD Only

MCM63F837/919–8.5

IDDA

—

—

TBD

mA

2, 3, 4

CMOS Standby Supply Current (Device Deselected, Freq = 0,

VDD = Max, All Inputs Static at CMOS Levels)

ISB2

—

—

TBD

mA

5, 6

Sleep Mode Supply Current (Device Deselected, Freq = Max,

VDD = Max, All Other Inputs Static at CMOS Levels,

ZZ

≥ VDD – 0.2 V)

IZZ

—

—

TBD

mA

1, 5, 6

TTL Standby Supply Current (Device Deselected, Freq = 0,

VDD = Max, All Inputs Static at TTL Levels)

ISB3

—

—

TBD

mA

5, 7

Clock Running (Device Deselected,

MCM63F837/919–7

Freq = Max, VDD = Max, All Inputs

MCM63F837/919–8

Toggling at CMOS Levels)

MCM63F837/919–8.5

ISB4

—

—

TBD

mA

5, 6

Static Clock Running (Device

MCM63F837/919–7

Deselected, Freq = Max, VDD = Max,

MCM63F837/919–8

All Inputs Static at TTL Levels)

MCM63F837/919–8.5

ISB5

—

—

TBD

mA

5, 7

NOTES:

1. LBO and ZZ pins have an internal pull–up and pull–down, and will exhibit leakage currents of

±5 µA.

2. Reference AC Operating Conditions and Characteristics for input and timing.

3. All addresses transition simultaneously low (LSB) then high (MSB).

4. Data states are all zero.

5. Device is deselected as defined by the Truth Table.

6. CMOS levels for I/Os are VIT ≤ VSS + 0.2 V or ≥ VDDQ – 0.2 V. CMOS levels for other inputs are Vin ≤ VSS + 0.2 V or ≥ VDD – 0.2 V.

7. TTL levels for I/Os are VIT ≤ VIL or ≥ VIH2. TTL levels for other inputs are Vin ≤ VIL or ≥ VIH.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com