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ICE2QR0665 Datasheet(PDF) 8 Page - Infineon Technologies AG |
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ICE2QR0665 Datasheet(HTML) 8 Page - Infineon Technologies AG |
8 / 21 page CoolSET ® - Q1 ICE2QR0665 Functional Description Version 2.3 8 April 27, 2010 after demagnetisation of the transformer. This value is fixed according to the feedback voltage, V FB, which contains information about the output power. Indeed, in a typical peak current mode control, a high output power results in a high feedback voltage, and a low output power leads to a low regulation voltage. Hence, according to V FB, the value in the up/down counter is changed to vary the power MOSFET off- time according to the output power. In the following, the variation of the up/down counter value according to the feedback voltage is explained. The feedback voltage V FB is internally compared with three threshold voltages V RL, VRH and VRM, at each clock period of 48ms. The up/down counter counts then upward, keep unchanged or count downward, as shown in Table 1. Table 1 Operation of the up/down counter In the ICE2QR0665, the number of zero crossing is limited to 7. Therefore, the counter varies between 1 and 7, and any attempt beyond this range is ignored. When V FB exceeds V FBR1 voltage, the up/down counter is initialised to 1, in order to allow the system to react rapidly to a sudden load increase. The up/down counter value is also intialised to 1 at the start-up, to ensure an efficient maximum load start up. Figure 5 shows some examples on how up/down counter is changed according to the feedback voltage over time. The use of two different thresholds V FBZL and VFBZH to count upward or downward is to prevent frequency jittereing when the feedback voltage is close to the threshold point. However, for a stable operation, these two thresholds must not be affected by the foldback current limitation (see Section 3.4.1), which limits the V CS voltage. Hence, to prevent such situation, the threshold voltages, V FBZL and V FBZH, are changed internally depending on the line voltage levels. Figure 5 Up/down counter operation 3.3.1.2 Zero crossing (ZC counter) In the system, the voltage from the auxiliary winding is applied to the zero-crossing pin through a RC network, which provides a time delay to the voltage from the auxiliary winding. Internally, this pin is connected to a clamping network, a zero-crossing detector, an output overvoltage detector and a ringing suppression time controller. During on-state of the power switch a negative voltage applies to the ZC pin. Through the internal clamping network, the voltage at the pin is clamped to certain level. The ZC counter has a minimum value of 0 and maximum value of 7. After the internal MOSFET is turned off, every time when the falling voltage ramp of on ZC pin crosses the 100mV threshold, a zero crossing is detected and ZC counter will increase by 1. It is reset every time after the DRIVER output is changed to high. The voltage v ZC is also used for the output overvoltage protection. Once the voltage at this pin is higher than the threshold V ZCOVP during off-time of the main switch, the IC is latched off after a fixed blanking time. To achieve the switch-on at voltage valley, the voltage from the auxiliary winding is fed to a time delay network (the RC network consists of D zc, Rzc1, Rzc2 and Czc as shown in typical application circuit) before it is applied to the zero-crossing detector through the ZC pin. The needed time delay to the main oscillation signal ∆t should be approximately one fourth of the oscillation period (by transformer primary inductor and drain- source capacitor) minus the propagation delay from v FB up/down counter action Always lower than V FBZL Count upwards till 7 Once higher than V FBZL, but always lower than V FBZH Stop counting, no value changing Once higher than V FBZH, but always lower than V FBR1 Count downwards till 1 Once higher than V FBR1 Set up/down counter to 1 1 Case 3 Case 2 Case 1 Up/down counter 4 5 6 6 6 6 5 4 3 1 1 2 3 4 4 4 4 3 2 1 7 7 7 7 7 7 6 5 4 t t VFB VFBR1 VFBZH VFBZL clock T=48ms 1 |
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