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W6811 Datasheet(PDF) 10 Page - Winbond |
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W6811 Datasheet(HTML) 10 Page - Winbond |
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10 / 37 page  W6811 Publication Release Date: September, 2005 - 10 - Revision A12 7.3. POWER MANAGEMENT 7.3.1. Analog Supply The power supply for the analog part of the W6811 needs to be 5V +/- 10%. This supply voltage is connected to the VDDA pin. The VDDA pin needs to be decoupled to ground through a 0.1 μF ceramic capacitor. 7.3.2. Digital Supply The power supply for the digital part of the W6811 needs to be 3V +/- 10%. This supply voltage is connected to the VDDD pin. The VDDD pin needs to be decoupled to ground through a 0.1 μF ceramic capacitor. 7.3.3. Analog Ground Reference Bypass The system has an internal precision voltage reference which generates the 2.5V mid-supply analog ground voltage. This voltage needs to be decoupled to VSSA at the VREF pin through a 0.1 μF ceramic capacitor. 7.3.4. Analog Ground Reference Voltage Output The analog ground reference voltage is available for external reference at the VAG pin. This voltage needs to be decoupled to VSSA through a 0.01 μF ceramic capacitor. The analog ground reference voltage is generated from the voltage on the VREF pin and is also used for the internal signal processing. 7.4. PCM INTERFACE The PCM interface is controlled by pins BCLKR, FSR, BCLKT & FST. The input data is received through the PCMR pin and the output data is transmitted through the PCMT pin. The modes of operation of the interface are shown in Table 7.3. BCLKR FSR Interface Mode 64 kHz to 4.096 MHz 8 kHz Long or Short Frame Sync VSSD VSSD ISDN GCI with active channel B1 VSSD VDDD ISDN GCI with active channel B2 VDDD VSSD ISDN IDL with active channel B1 VDDD VDDD ISDN IDL with active channel B2 Table 7.3 PCM Interface mode selections 7.4.1. Long Frame Sync The Long Frame Sync or Short Frame Sync interface mode can be selected by connecting the BCLKR or BCLKT pin to a 64 kHz to 4.096 MHz clock and connecting the FSR or FST pin to the 8 kHz frame sync. The device synchronizes the data word for the PCM interface and the CODEC sample rate on the positive edge of the Frame Sync signal. It recognizes a Long Frame Sync when the FST pin is |
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