W78E54B/W78E054B

Publication Release Date: August 14, 2006

- 7 -

Revision A6

6. FUNCTIONAL DESCRIPTION

The W78E54B architecture consists of a core controller surrounded by various registers, five general

purpose I/O ports, 256 bytes of RAM, three timer/counters, and a serial port. The processor supports

111 different opcodes and references both a 64K program address space and a 64K data storage

space.

6.1 Timers 0, 1, and 2

Timers 0, 1, and 2 each consist of two 8-bit data registers. These are called TL0 and TH0 for Timer 0,

TL1 and TH1 for Timer 1, and TL2 and TH2 for Timer 2. The TCON and TMOD registers provide

control functions for timers 0 and 1. The T2CON register provides control functions for Timer 2.

RCAP2H and RCAP2L are used as reload/capture registers for Timer 2.

The operations of Timer 0 and Timer 1 are the same as in the W78C51. Timer 2 is a special feature of

the W78E54B: it is a 16-bit timer/counter that is configured and controlled by the T2CON register. Like

Timers 0 and 1, Timer 2 can operate as either an external event counter or as an internal timer,

depending on the setting of bit C/T2 in T2CON. Timer 2 has three operating modes: capture, auto-

reload, and baud rate generator. The clock speed at capture or auto-reload mode is the same as that

of Timers 0 and 1.

6.2 New Defined Peripheral

In order to be more suitable for I/O, an extra 4-bit bit-addressable port P4 and two external interrupt

INT2

6.2.1

INT2

interrupt 0 and 1 in the standard 80C52. The functions/status of these interrupts are

determined/shown by the bits in the XICON (External Interrupt Control) register. The XICON register is

bit-addressable but is not a standard register in the standard 80C52. Its address is at 0C0H. To

set/clear bits in the XICON register, one can use the "SETB (/CLR) bit" instruction. For example,

"SETB 0C2H" sets the EX2 bit of XICON.

XICON - external interrupt control (C0H)

PX3

EX3

IE3

IT3

PX2

EX2

IE2

IT2

PX3: External interrupt 3 priority high if set

EX3: External interrupt 3 enable if set

IE3: If IT3 = 1, IE3 is set/cleared automatically by hardware when interrupt is detected/serviced

IT3: External interrupt 3 is falling-edge/low-level triggered when this bit is set/cleared by software

PX2: External interrupt 2 priority high if set

EX2: External interrupt 2 enable if set

IE2: If IT2 = 1, IE2 is set/cleared automatically by hardware when interrupt is detected/serviced

IT2: External interrupt 2 is falling-edge/low-level triggered when this bit is set/cleared by software