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W78C032C40FL Datasheet(PDF) 10 Page - Winbond |
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W78C032C40FL Datasheet(HTML) 10 Page - Winbond |
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10 / 18 page  W78C32C/W78C032C - 10 - 6.3.2 Program Fetch Cycle PARAMETER SYMBOL MIN. TYP. MAX. UNIT NOTES Address Valid to ALE Low TAAS 1 TCP- Δ - - nS 4 Address Hold after ALE Low TAAH 1 TCP- Δ - - nS 1, 4 ALE Low to PSEN Low TAPL 1 TCP- Δ - - nS 4 PSEN Low to Data Valid TPDA - - 2 TCP nS 2 Data Hold after PSEN High TPDH 0 - 1 TCP nS 3 Data Float after PSEN High TPDZ 0 - 1 TCP nS ALE Pulse Width TALW 2 TCP- Δ 2 TCP - nS 4 PSEN Pulse Width TPSW 3 TCP- Δ 3 TCP - nS 4 Notes: 1. P0.0 −P0.7, P2.0−P2.7 remain stable throughout entire memory cycle. 2. Memory access time is 3 TCP. 3. Data have been latched internally prior to PSEN going high. 4. " Δ" ( due to buffer driving delay and wire loading) is 20 nS. 6.3.3 Data Read Cycle PARAMETER SYMBOL MIN. TYP. MAX. UNIT NOTES ALE Low to RD Low TDAR 3 TCP- Δ - 3 TCP+ Δ nS 1, 2 RD Low to Data Valid TDDA - - 4 TCP nS 1 Data Hold after RD High TDDH 0 - 2 TCP nS Data Float after RD High TDDZ 0 - 2 TCP nS RD Pulse Width TDRD 6 TCP- Δ 6 TCP - nS 2 Notes: 1. Data memory access time is 8 TCP. 2. " Δ" (due to buffer driving delay and wire loading) is 20 nS. |
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