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W77L058A25PL Datasheet(PDF) 11 Page - Winbond |
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W77L058A25PL Datasheet(HTML) 11 Page - Winbond |
11 / 82 page W77LE58/W77L058A Publication Release Date: February 1, 2007 - 11 - Revision A7 Power Control Bit: 7 6 5 4 3 2 1 0 SM0D SMOD0 - - GF1 GF0 PD IDL Mnemonic: PCON Address: 87h SMOD : This bit doubles the serial port baud rate in mode 1, 2, and 3 when set to 1. SMOD0: Framing Error Detection Enable: When SMOD0 is set to 1, then SCON.7(SCON1.7) indicates a Frame Error and acts as the FE(FE_1) flag. When SMOD0 is 0, then SCON.7(SCON1.7) acts as per the standard 8052 function. GF1-0: These two bits are general purpose user flags. PD: Setting this bit causes the W77L058 to go into the POWER DOWN mode. In this mode all the clocks are stopped and program execution is frozen. IDL: Setting this bit causes the W77L058 to go into the IDLE mode. In this mode the clocks to the CPU are stopped, so program execution is frozen. But the clock to the serial, timer and interrupt blocks is not stopped, and these blocks continue operating. Timer Condtrol Bit: 7 6 5 4 3 2 1 0 TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 Mnemonic: TCON Address: 88h TF1: Timer 1 overflow flag: This bit is set when Timer 1 overflows. It is cleared automatically when the program does a timer 1 interrupt service routine. Software can also set or clear this bit. TR1: Timer 1 run control: This bit is set or cleared by software to turn timer/counter on or off. TF0: Timer 0 overflow flag: This bit is set when Timer 0 overflows. It is cleared automatically when the program does a timer 0 interrupt service routine. Software can also set or clear this bit. TR0: Timer 0 run control: This bit is set or cleared by software to turn timer/counter on or off. IE1: Interrupt 1 edge detect: Set by hardware when an edge/level is detected on INT1. This bit is cleared by hardware when the service routine is vectored to only if the interrupt was edge triggered. Otherwise it follows the pin. IT1: Interrupt 1 type control: Set/cleared by software to specify falling edge/ low level triggered external inputs. IE0: Interrupt 0 edge detect: Set by hardware when an edge/level is detected on 1 INT . This bit is cleared by hardware when the service routine is vectored to only if the interrupt was edge triggered. Otherwise it follows the pin. IT0: Interrupt 0 type control: Set/cleared by software to specify falling edge/ low level triggered external inputs. |
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