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W77IE58 Datasheet(PDF) 4 Page - Winbond |
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W77IE58 Datasheet(HTML) 4 Page - Winbond |
4 / 82 page W77IE58/W77I058A - 4 - 4. PIN DESCRIPTION SYMBOL TYPE DESCRIPTIONS EA I EXTERNAL ACCESS ENABLE: This pin forces the processor to execute out of external ROM. It should be kept high to access internal ROM. The ROM address and data will not be present on the bus if EA pin is high and the program counter is within 32 KB area. Otherwise they will be present on the bus. PSEN O PROGRAM STORE ENABLE: PSEN enables the external ROM data onto the Port 0 address/data bus during fetch and MOVC operations. When internal ROM access is performed, no PSEN strobe signal outputs from this pin. ALE O ADDRESS LATCH ENABLE: ALE is used to enable the address latch that separates the address from the data on Port 0. RST I RESET: A high on this pin for two machine cycles while the oscillator is running resets the device. XTAL1 I CRYSTAL1: This is the crystal oscillator input. This pin may be driven by an external clock. XTAL2 O CRYSTAL2: This is the crystal oscillator output. It is the inversion of XTAL1. VSS I GROUND: Ground potential VDD I POWER SUPPLY: Supply voltage for operation. P0.0 −P0.7 I/O PORT 0: Port 0 is an open-drain bi-directional I/O port. This port also provides a multiplexed low order address/data bus during accesses to external memory. P1.0 −P1.7 I/O PORT 1: Port 1 is a bi-directional I/O port with internal pull-ups. The bits have alternate functions which are described below: T2(P1.0): Timer/Counter 2 external count input T2EX(P1.1): Timer/Counter 2 Reload/Capture/Direction control RXD1(P1.2): Serial port 2 RXD TXD1(P1.3): Serial port 2 TXD INT2(P1.4): External Interrupt 2 INT3 (P1.5): External Interrupt 3 INT4 (P1.6): External Interrupt 4 INT5 (P1.7): External Interrupt 5 P2.0 −P2.7 I/O PORT 2: Port 2 is a bi-directional I/O port with internal pull-ups. This port also provides the upper address bits for accesses to external memory. |
Similar Part No. - W77IE58_06 |
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Similar Description - W77IE58_06 |
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