Applications Information

PCLKIN Latch Edge

The parallel data input of the MAX9225 serializer is

latched on the rising edge of PCLKIN. Figure 3 shows

the serializer input timing.

PCLKOUT Strobe

The serial-data output of the MAX9226 deserializer is

valid on the rising edge of PCLKOUT. Figure 4 shows

the deserializer output timing.

Power-Down and Power-Up

Driving PWRDN low puts the MAX9225 in power-down

mode and sends a pulse to power down the MAX9226.

In power-down mode, the DLL is stopped, SDO+/SDO-

are high impedance to ground and differential, and the

PWRDN and all inputs low, the combined MAX9225/

MAX9226 supply current is reduced to 3.5µA or less.

Driving PWRDN high starts DLL lock to PCLKIN and ini-

tiates a MAX9226 power-up sequence. The MAX9225

LCDS output is not driven until the DLL locks. 11,264

clock cycles are required for the power-up and link syn-

chronization before valid DIN can be latched. See

Figure 6 for an overall power-up and power-down tim-

ing diagram. For normal operation, PCLKIN must be

running and settled before driving PWRDN high.

ground and differential.

Ground-Shift Tolerance

The MAX9225/MAX9226 are designed to function nor-

mally in the event of a slight shift in ground potential.

However, the MAX9226 deserializer ground must be

within ±0.2V relative to the MAX9225 serializer ground

to maintain proper operation.

which accepts a +1.71V to +3.465V supply, allowing

direct interface to inputs with 1.8V to 3.3V logic levels.

10-Bit, Low-Power, 10MHz-to-20MHz

Serializer and Deserializer Chipset

10

______________________________________________________________________________________

DIN[9:0]

PCLK IN

DIN

EXAMPLE

INPUT

PARALLEL DATA INPUT

LCDS SERIAL-DATA OUTPUT FOR EXAMPLE INPUT (SD0+/SDO-)

NOTE: OH1 AND OH2 ARE OPPOSITE POLARITY.

OH1

OH2

1

1

1

11

1

00

0

0

01

2

3

4

5

6

7

8

9

11

0

1

0

0

1

0

1

1

Figure 5. Multilevel LCDS Output Representation