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ATR0622-DK1 Datasheet(PDF) 9 Page - ATMEL Corporation

Part # ATR0622-DK1
Description  GPS Baseband GPS Baseband
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Manufacturer  ATMEL [ATMEL Corporation]
Direct Link  http://www.atmel.com
Logo ATMEL - ATMEL Corporation

ATR0622-DK1 Datasheet(HTML) 9 Page - ATMEL Corporation

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9
4890H–GPS–08/08
ATR0621P
3.2
Signal Description
Table 3-2.
ATR0621P Signal Description
Module
Name
Function
Type
Active Level Comment
EBI
EM_A0 to EM_A21
External memory address bus
Output
All valid after reset
EM_DA0 to EM_DA15 External memory data bus
I/O
Internal pull-down resistor
NCS0 to NCS1
Chip select
Output
Low
Output high in RESET state
NCS2 to NCS3
Chip select
Output
Low
Output high in RESET state
NWR0
Lower byte write signal
Output
Low
Output high in RESET state
NWR1
Upper byte write signal
Output
Low
Output high in RESET state
NRD
Read signal
Output
Low
Output high in RESET state
NWE
Write enable
Output
Low
Output high in RESET state
NOE
Output enable
Output
Low
Output high in RESET state
NUB
Upper byte select (16-bit SRAM)
Output
Low
Output high in RESET state
NLB
Lower byte select (16-bit SRAM)
Output
Low
Output high in RESET state
BOOT_MODE
Boot mode input
Input
PIO-controlled after reset,
internal pull-down resistor
USART
TXD1-2
Transmit data output
Output
PIO-controlled after reset
RXD1-2
Receive data input
Input
PIO-controlled after reset
SCK1-2
External synchronous serial clock
I/O
PIO-controlled after reset
USB
USB_DP
USB data (D+)
I/O
USB_DM
USB data (D-)
I/O
APMC
RF_ON
Output
Interface to ATR0601
AIC
EXTINT0-1
External interrupt request
Input
High/
Low/
Edge
PIO-controlled after reset
AGC
AGCOUT0-1
Automatic gain control
Output
Interface to ATR0601
PIO-controlled after reset
RTC
NSLEEP
Sleep output
Output
Low
Interface to ATR0601
NSHDN
Shutdown output
Output
Low
Connect to pin LDO_EN
XT_IN
Oscillator input
Input
RTC oscillator
XT_OUT
Oscillator output
Output
RTC oscillator
SPI
SCK
SPI clock
I/O
PIO-controlled after reset
MOSI
Master out slave in
I/O
PIO-controlled after reset
MISO
Master in slave out
I/O
PIO-controlled after reset
NSS/NPCS0
Slave select
I/O
Low
PIO-controlled after reset
NPCS1-3
Slave select
Output
Low
PIO-controlled after reset
WD
NWD_OVF
Watchdog timer overflow
Output
PIO-controlled after reset
PIO
P0-31
Programmable I/O port
I/O
Input after reset
(except P3 to P7, P10, P11, P28)
Note:
1. The USB transceiver is disabled if VDD_USB < 2.0V. In this case the pins USB_DM and USB_DP are connected to GND
(internal pull-down resistors). The USB transceiver is enabled if VDD_USB is within 3.0V and 3.6V.


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