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AT85SND3B1-RTTUL Datasheet(PDF) 9 Page - ATMEL Corporation |
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AT85SND3B1-RTTUL Datasheet(HTML) 9 Page - ATMEL Corporation |
9 / 271 page 9 AT85C51SND3B 7632D–MP3–01/07 Table 3. Timer 0 and Timer 1 Signal Description P4.6:0 I/O Port 4 P4 is a 7-bit bidirectional I/O port with internal pull-ups. OCLK DCLK DDAT DSEL NFCE1/SMLCK NFCE2/SMINS NFCE3/SMCE P5.3:0 I/O Port 5 P5 is a 4-bit bidirectional I/O port with internal pull-ups. LRD/LDE SDR LCS SCS LA0/LRS SA0 LWR/LRW SWR Signal Name Type Description Alternate Function INT0 I Timer 0 Gate Input INT0 serves as external run control for timer 0, when selected by GATE0 bit in TCON register. External Interrupt 0 INT0 input sets IE0 in the TCON register. If bit IT0 in this register is set, bit IE0 is set by a falling edge on INT0. If bit IT0 is cleared, bit IE0 is set by a low level on INT0. P3.2 RTS SCK INT1 I Timer 1 Gate Input INT1 serves as external run control for timer 1, when selected by GATE1 bit in TCON register. External Interrupt 1 INT1 input sets IE1 in the TCON register. If bit IT1 in this register is set, bit IE1 is set by a falling edge on INT1. If bit IT1 is cleared, bit IE1 is set by a low level on INT1. P3.3 CTS SS T0 I Timer 0 External Clock Input When timer 0 operates as a counter, a falling edge on the T0 pin increments the count. P3.4 Signal Name Type Description Alternate Function |
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