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CY8C20160-LDX2I Datasheet(PDF) 3 Page - Cypress Semiconductor |
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CY8C20160-LDX2I Datasheet(HTML) 3 Page - Cypress Semiconductor |
3 / 29 page CY8C20110/CY8C20180/CY8C20160 CY8C20140/CY8C20142 Document Number: 001-54606 Rev. ** Page 3 of 29 Figure 2. Pin Diagram – 16 SOIC– CY8C20110 (10 Buttons)/CY8C20180 (8 Buttons) CY8C20160 (6 Buttons)/CY8C20140 (4 Buttons) Table 2. Pin Definitions – 16 SOIC– CY8C20110 (10 Buttons)/CY8C20180 (8 Buttons) CY8C20160 (6 Buttons)/CY8C20140 (4 Buttons)1] Pin No Name Description 1 GP0[3] Configurable as CapSense or GPIO 2 CSint Integrating Capacitor Input. The external capacitance is required only if 5:1 SNR cannot be achieved. Typical range is 1 nF to 4.7 nF 3 GP0[4] Configurable as CapSense or GPIO 4 GP0[0] Configurable as CapSense or GPIO 5 GP0[1] Configurable as CapSense or GPIO 6I2C SCL I2C Clock 7I2C SDA I2C Data 8 GP1[0] Configurable as CapSense or GPIO 9 GP1[1] Configurable as CapSense or GPIO 10 VSS Ground Connection 11 GP1[2] Configurable as CapSense or GPIO 12 GP1[3] Configurable as CapSense or GPIO 13 GP1[4] Configurable as CapSense or GPIO 14 XRES Active high external reset with internal pull up 15 GP0[2] Configurable as CapSense or GPIO 16 VDD Supply voltage [+] Feedback [+] Feedback |
Similar Part No. - CY8C20160-LDX2I |
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Similar Description - CY8C20160-LDX2I |
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