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CY7C0832AV-133BBI Datasheet(PDF) 5 Page - Cypress Semiconductor |
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CY7C0832AV-133BBI Datasheet(HTML) 5 Page - Cypress Semiconductor |
5 / 28 page CY7C0837AV, CY7C0830AV CY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV Document #: 38-06059 Rev. *S Page 5 of 28 Pin Definitions Left Port Right Port Description A0L–A18L [2] A0R–A18R [2] Address Inputs. ADSL [8] ADSR [8] Address Strobe Input. Used as an address qualifier. This signal should be asserted LOW for the part using the externally supplied address on the address pins and for loading this address into the burst address counter. CE0L [8] CE0R [8] Active LOW Chip Enable Input. CE1L [7] CE1R [7] Active HIGH Chip Enable Input. CLKL CLKR Clock Signal. Maximum clock input rate is fMAX. CNTENL [8] CNTENR [8] Counter Enable Input. Asserting this signal LOW increments the burst address counter of its respective port on each rising edge of CLK. The increment is disabled if ADS or CNTRST are asserted LOW. CNTRSTL [7] CNTRSTR [7] Counter Reset Input. Asserting this signal LOW resets to zero the unmasked portion of the burst address counter of its respective port. CNTRST is not disabled by asserting ADS or CNTEN. CNT/MSKL [7] CNT/MSKR [7] Address Counter Mask Register Enable Input. Asserting this signal LOW enables access to the mask register. When tied HIGH, the mask register is not accessible and the address counter operations are enabled based on the status of the counter control signals. DQ0L–DQ17L DQ0R–DQ17R Data Bus Input/Output. OEL OER Output Enable Input. This asynchronous signal must be asserted LOW to enable the DQ data pins during Read operations. INTLINTR Mailbox Interrupt Flag Output. The mailbox permits communications between ports. The upper two memory locations are used for message passing. INTL is asserted LOW when the right port writes to the mailbox location of the left port, and vice versa. An interrupt to a port is deasserted HIGH when it reads the contents of its mailbox. CNTINTL [9] CNTINTR [9] Counter Interrupt Output. This pin is asserted LOW when the unmasked portion of the counter is incremented to all ‘1s.’ R/WL R/WR Read/Write Enable Input. Assert this pin LOW to write to, or HIGH to Read from the dual port memory array. B0L–B1L B0R–B1R Byte Select Inputs. Asserting these signals enables Read and Write operations to the corre- sponding bytes of the memory array. MRST Master Reset Input. MRST is an asynchronous input signal and affects both ports. Asserting MRST LOW performs all of the reset functions as described in the text. A MRST operation is required at power up. TMS JTAG Test Mode Select Input. It controls the advance of JTAG TAP state machine. State machine transitions occur on the rising edge of TCK. TDI JTAG Test Data Input. Data on the TDI input is shifted serially into selected registers. TCK JTAG Test Clock Input. TDO JTAG Test Data Output. TDO transitions occur on the falling edge of TCK. TDO is normally three-stated except when captured data is shifted out of the JTAG TAP. VSS Ground Inputs. VDD Power Inputs. Byte Select Operation Control Pin Effect B0 DQ0–8 Byte Control B1 DQ9–17 Byte Control [+] Feedback |
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