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CY8CPLC10 Datasheet(PDF) 3 Page - Cypress Semiconductor |
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CY8CPLC10 Datasheet(HTML) 3 Page - Cypress Semiconductor |
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3 / 25 page  CY8CPLC10 Document Number: 001-50001 Rev. *D Page 3 of 25 Transmitter Section Digital data from the network layer is serialized by the digital transmitter and fed as input to the modulator. The modulator divides the local oscillator frequency by a definite factor depending on whether the input data is high level logic ‘1’ or low level logic ‘0’. It then generates a sine wave at 133.3 kHz (Logic ‘0’) or 131.8 kHz (Logic ‘1’), which is fed to the Programmable Gain Amplifier to generate FSK modulated signals. The logic ‘1’ frequency can also be configured as 130.4 kHz for wider FSK bandwidth. The device also provides a provision to bypass the internal TX filter and output a square wave at the respective FSK frequencies. Receiver Section The incoming FSK signal from the Powerline is input to a High Frequency (HF) Band Pass Filter that filters out-of-band frequency components and outputs filtered signal within the desired spectrum of 125 kHz to 140 kHz for further demodu- lation. The Mixer block multiplies the filtered FSK signals with a locally generated signal to produce heterodyned frequencies. The Intermediate Frequency (IF) Band Pass Filters further remove out-of-band noise as required for further demodulation. This signal is fed to the correlator which produces a DC component (consisting of Logic ‘1’ and ‘0’) and a higher frequency component. The output of the correlator is fed to a Low Pass FIlter (LPF) that outputs only the demodulated digital data at 2400 baud and suppresses all other higher frequency components generated in the correlation process. The output of the LPF is digitized by the hysteresis comparator. This eliminates the effects of correlator delay and false logic triggers due to noise. The Digital Receiver deserializes this data and outputs to the Network Layer for inter- pretation. The receiver also implements Automatic Gain Control (AGC). This functionality enables the receiver to adjust its gain automat- ically depending on the signal strength of the input FSK signal. Coupling Circuit Reference Design The coupling circuit couples low voltage signals from CY8CPLC10 to the Powerline. The topology of this circuit is determined by the voltage on the Powerline and design constraints mandated by Powerline usage regulations. Cypress provides reference designs for a range of Powerline voltages such as 110V AC, 240V AC, 12V DC, 24V DC, and 24V AC. The 110V AC and 240V AC designs are compliant to the following Powerline usage regulations: ■ FCC part 15 for North America ■ EN50065-1:2001 Powerline Network Protocol Cypress’s Powerline optimized Network Protocol performs the functions of the data link, network, and transport layers in an ISO/OSI Equivalent Model. Figure 4. CY8CPLC10: Powerline Network Protocol The Network Protocol implemented on the CY8CPLC10 chip supports the following features: ■ Bidirectional half-duplex communication ■ Master and slave and peer-to-peer network of Powerline nodes ■ Multiple masters on Powerline network ■ 8-bit logical addressing supports up to 256 Powerline nodes ■ 16-bit extended logical addressing supports up to 65530 Powerline nodes ■ 64-bit physical addressing supports up to 264 Powerline nodes ■ Individual broadcast or group mode addressing ■ Carrier Sense Multiple Access (CSMA) ■ Full control over transmission parameters ❐ Acknowledged ❐ Unacknowledged ❐ Repeated transmit ❐ Sequence numbering CSMA and Timing Parameters ■ CSMA: The protocol provides the random selection of a period between 85 and 115 ms (out of seven possible values in this range) in which the band in use detector must indicate that the line is not in use, before attempting a transmission ■ Band-In-Use (BIU): A Band-In-Use detector, as defined under CENELEC EN 50065-1, is active whenever a signal that exceeds 86 dBuVrms in the range 131.5 KHz to 133.5 KHz is present for at least 4 ms. This threshold can be configured for different end-system applications not requiring CENELEC compliance.The modem tries to retransmit after every 85 to 115 ms when the Band is in use. The Transmitter times out after 1.1 seconds and generates an interrupt to indicate that the transmitter was unable to acquire the Powerline. I2C Packet Powerline Network Protocol Powerline FSK Modem PHY Powerline Communication Solution [+] Feedback |
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