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CY7C1311JV18-300BZXC Datasheet(PDF) 9 Page - Cypress Semiconductor |
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CY7C1311JV18-300BZXC Datasheet(HTML) 9 Page - Cypress Semiconductor |
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9 / 27 page  CY7C1311JV18/CY7C1911JV18 CY7C1313JV18/CY7C1315JV18 Document Number: 001-12562 Rev. *D Page 9 of 27 Concurrent Transactions The read and write ports on the CY7C1311JV18 operate indepen- dently of one another. As each port latches the address inputs on different clock edges, the user reads or writes to any location, regardless of the transaction on the other port. If the ports access the same location when a read follows a write in successive clock cycles, the SRAM delivers the most recent information associated with the specified address location. This includes forwarding data from a write cycle that was initiated on the previous K clock rise. Schedule read accesses and write access such that one transaction is initiated on any clock cycle. If both ports are selected on the same K clock rise, the arbitration depends on the previous state of the SRAM. If both ports were deselected, the read port takes priority. If a read was initiated on the previous cycle, the write port takes priority (as read operations cannot be initiated on consecutive cycles). If a write was initiated on the previous cycle, the read port takes priority (as write operations cannot be initiated on consecutive cycles). Therefore, asserting both port selects active from a deselected state results in alternating read or write operations being initiated, with the first access being a read. Depth Expansion The CY7C1311JV18 has a port select input for each port. This enables easy depth expansion. Both port selects are sampled on the rising edge of the positive input clock only (K). Each port select input deselects the specified port. Deselecting a port does not affect the other port. All pending transactions (read and write) are completed before the device is deselected. Programmable Impedance Connect an external resistor, RQ, between the ZQ pin on the SRAM and VSS to enable the SRAM to adjust its output driver impedance. The value of RQ is five times the value of the intended line impedance driven by the SRAM. The allowable range of RQ to guarantee impedance matching with a tolerance of ±15 percent is between 175 Ω and 350Ω, with V DDQ =1.5V. The output impedance is adjusted every 1024 cycles upon power up to account for drifts in supply voltage and temperature. Echo Clocks Echo clocks are provided on the QDR II to simplify data capture on high speed systems. Two echo clocks are generated by the QDR II. CQ is referenced with respect to C and CQ is referenced with respect to C. These are free running clocks and are synchronized to the output clock of the QDR II. In single clock mode, CQ is generated with respect to K and CQ is generated with respect to K. The timing for the echo clocks is shown in the Switching Characteristics on page 23. DLL These chips use a DLL that is designed to function between 120 MHz and the specified maximum clock frequency. During power up, when the DOFF is tied HIGH, the DLL is locked after 1024 cycles of stable clock. The DLL is also reset by slowing or stopping the input clock K and K for a minimum of 30 ns. However, it is not necessary to reset the DLL to lock to the desired frequency. The DLL automatically locks 1024 clock cycles after a stable clock is presented. Disable the DLL by applying ground to the DOFF pin. When the DLL is turned off, the device behaves in QDR I mode (with one cycle latency and a longer access time). For information refer to the application note DLL Considerations in QDRII/DDRII. [+] Feedback |
Similar Part No. - CY7C1311JV18-300BZXC |
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Similar Description - CY7C1311JV18-300BZXC |
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