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CY7C1480BV33-167BZC Datasheet(PDF) 7 Page - Cypress Semiconductor |
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CY7C1480BV33-167BZC Datasheet(HTML) 7 Page - Cypress Semiconductor |
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7 / 34 page  CY7C1480BV33 CY7C1482BV33, CY7C1486BV33 Document #: 001-15145 Rev. *A Page 7 of 34 Pin Definitions Pin Name IO Description A0, A1, A Input- Synchronous Address Inputs used to Select One of the Address Locations. Sampled at the rising edge of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A1: A0 are fed to the 2-bit counter. BWA,BWB,BWC,BWD, BWE,BWF,BWG,BWH Input- Synchronous Byte Write Select Inputs, Active LOW. Qualified with BWE to conduct byte writes to the SRAM. Sampled on the rising edge of CLK. GW Input- Synchronous Global Write Enable Input, Active LOW. When asserted LOW on the rising edge of CLK, a global write is conducted (all bytes are written, regardless of the values on BWX and BWE). BWE Input- Synchronous Byte Write Enable Input, Active LOW. Sampled on the rising edge of CLK. This signal must be asserted LOW to conduct a byte write. CLK Input- Clock Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the burst counter when ADV is asserted LOW during a burst operation. CE1 Input- Synchronous Chip Enable 1 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2 and CE3 to select or deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is sampled only when a new external address is loaded. CE2 Input- Synchronous Chip Enable 2 Input, Active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE3 to select or deselect the device. CE2 is sampled only when a new external address is loaded. CE3 Input- Synchronous Chip Enable 3 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE2 to select or deselect the device. CE3 is sampled only when a new external address is loaded. OE Input- Asynchronous Output Enable, Asynchronous Input, Active LOW. Controls the direction of the IO pins. When LOW, the IO pins behave as outputs. When deasserted HIGH, IO pins are tri-stated, and act as input data pins. OE is masked during the first clock of a read cycle when emerging from a deselected state. ADV Input- Synchronous Advance Input Signal, Sampled on the Rising Edge of CLK, Active LOW. When asserted, it automatically increments the address in a burst cycle. ADSP Input- Synchronous Address Strobe from Processor, Sampled on the Rising Edge of CLK, Active LOW. When asserted LOW, addresses presented to the device are captured in the address registers. A1: A0 are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE1 is deasserted HIGH. ADSC Input- Synchronous Address Strobe from Controller, Sampled on the Rising Edge of CLK, Active LOW. When asserted LOW, addresses presented to the device are captured in the address registers. A1: A0 are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ZZ Input- Asynchronous ZZ “Sleep” Input, Active HIGH. When asserted HIGH, places the device in a non-time-critical “sleep” condition with data integrity preserved. For normal operation, this pin must be LOW or left floating. ZZ pin has an internal pull down. DQs, DQPs IO- Synchronous Bidirectional Data IO Lines. As inputs, they feed into an on-chip data register that is triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the addresses presented during the previous clock rise of the read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQPX are placed in a tri-state condition. VDD Power Supply Power Supply Inputs to the Core of the Device. VSS Ground Ground for the Core of the Device. VSSQ [1] IO Ground Ground for the IO Circuitry. VDDQ IO Power Supply Power supply for the IO circuitry. Note 1. Applicable for TQFP package. For BGA package VSS serves as ground for the core and the IO circuitry. [+] Feedback |
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