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MUN5212DW1T1G Datasheet(PDF) 1 Page - ON Semiconductor |
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MUN5212DW1T1G Datasheet(HTML) 1 Page - ON Semiconductor |
1 / 20 page © Semiconductor Components Industries, LLC, 2009 October, 2009 − Rev. 8 1 Publication Order Number: MUN5211DW1T1/D MUN5211DW1T1G Series Preferred Devices Dual Bias Resistor Transistors NPN Silicon Surface Mount Transistors with Monolithic Bias Resistor Network The Bias Resistor Transistor (BRT) contains a single transistor with a monolithic bias network consisting of two resistors; a series base resistor and a base−emitter resistor. These digital transistors are designed to replace a single device and its external resistor bias network. The BRT eliminates these individual components by integrating them into a single device. In the MUN5211DW1T1G series, two BRT devices are housed in the SOT−363 package which is ideal for low power surface mount applications where board space is at a premium. Features • Simplifies Circuit Design • Reduces Board Space • Reduces Component Count • These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant MAXIMUM RATINGS (TA = 25°C unless otherwise noted, common for Q1 and Q2) Rating Symbol Value Unit Collector-Base Voltage VCBO 50 Vdc Collector-Emitter Voltage VCEO 50 Vdc Collector Current IC 100 mAdc THERMAL CHARACTERISTICS Characteristic (One Junction Heated) Symbol Max Unit Total Device Dissipation TA = 25°C Derate above 25°C PD 187 (Note 1) 256 (Note 2) 1.5 (Note 1) 2.0 (Note 2) mW mW/°C Thermal Resistance, Junction-to-Ambient RqJA 670 (Note 1) 490 (Note 2) °C/W Characteristic (Both Junctions Heated) Symbol Max Unit Total Device Dissipation TA = 25°C Derate above 25°C PD 250 (Note 1) 385 (Note 2) 2.0 (Note 1) 3.0 (Note 2) mW mW/°C Thermal Resistance, Junction-to-Ambient RqJA 493 (Note 1) 325 (Note 2) °C/W Thermal Resistance, Junction-to-Lead RqJL 188 (Note 1) 208 (Note 2) °C/W Junction and Storage Temperature TJ, Tstg −55 to +150 °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. FR−4 @ Minimum Pad 2. FR−4 @ 1.0 x 1.0 inch Pad Preferred devices are recommended choices for future use and best overall value. http://onsemi.com Q1 R1 R2 R2 R1 Q2 (1) (2) (3) (4) (5) (6) DEVICE MARKING INFORMATION See specific marking information in the device marking table on page 2 of this data sheet. SOT−363 CASE 419B STYLE 1 MARKING DIAGRAM xx M G G 1 6 xx = Device Code M = Date Code* G = Pb−Free Package (Note: Microdot may be in either location) *Date Code orientation and/or position may vary depending upon manufacturing location. 1 |
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