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FS7140-02G-XTP Datasheet(PDF) 3 Page - ON Semiconductor |
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FS7140-02G-XTP Datasheet(HTML) 3 Page - ON Semiconductor |
3 / 19 page FS714x Table 2: FS7145 Pin Descriptions Pin Type Name Description 1 DI SCL Serial interface clock (requires an external pull-up) 2 DIO SDA Serial interface data input/output (requires an external pull-up) 3 DID ADDR0 Address select bit “0” 4 P VSS Ground 5 AI XIN Crystal oscillator feedback 6 AO XOUT Crystal oscillator drive 7 DID ADDR1 Address select bit “1” 8 P VDD Power supply (+3.3V nominal) 9 AI IPRG PECL current drive programming 10 - n/c No connection 11 P VSS Ground 12 DI U REF Reference frequency input 13 DI U SYNC Synchronization input 14 P VDD Power supply (+3.3V nominal) 15 DO CLKP Clock output 16 DO CLKN Inverted clock output Key: AI: Analog Input; AO = Analog Output; DI = Digital Input; DI U = Input with Internal Pull-up; DID = Input with Internal Pull-down; DIO = Digital Input/Output; DI-3 = Three-Level Digital Input; DO = Digital Output; P = Power/Ground; # = Active Low Pin 4.0 Functional Block Diagram 4.1 Phase Locked Loop (PLL) The PLL is a standard phase- and frequency-locked loop architecture. The PLL consists of a reference divider, a phase-frequency detector (PFD), a charge pump, an internal loop filter, a voltage-controlled oscillator (VCO), a feedback divider, and a post divider. The reference frequency (generated by either the on-board crystal oscillator or an external frequency source), is first reduced by the reference divider. The integer value that the frequency is divided by is called the modulus and is denoted as NR for the reference divider. This divided reference is then fed into the PFD. The VCO frequency is fed back to the PFD through the feedback divider (the modulus is denoted by NF). The PFD will drive the VCO up or down in frequency until the divided reference frequency and the divided VCO frequency appearing at the inputs of the PFD are equal. The input/output relationship between the reference frequency and the VCO frequency is then: This basic PLL equation can be rewritten as A post divider (actually a series combination of three post dividers) follows the PLL and the final equation for device output frequency is: Rev. 5 | Page 3 of 19 | www.onsemi.com |
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