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315038-003US Datasheet(PDF) 11 Page - Intel Corporation |
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315038-003US Datasheet(HTML) 11 Page - Intel Corporation |
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11 / 89 page  Intel® 81348 I/O Processor December 2007 Datasheet Order Number: 315038-003US 11 Features—Intel® 81348 2.2 Intel® 81348 I/O Processor Features The 81348 combines two Intel XScale® processors with powerful new features to create an intelligent I/O storage processor. This single- or dual-function PCI device is fully compliant with the PCI-X Addendum to the PCI Local Bus Specification, Revision 2.0 and PCI Express Specification, Revision 1.0. Features specific to 81348 include the following: The 81348 is based upon two Intel XScale® processors. The processor operates at a maximum frequency of 1.2 GHz. The instruction cache is 32 Kbytes in size and is 4-way set associative. Also, the processor includes a data cache that is 32 Kbytes and is 4- way set associative. The Intel XScale® processors also support a unified 512-Kbyte Level 2 (L2) cache that is 8-way set associative. The 81348 includes sixteen General Purpose I/O (GPIO) pins, and eight ACTIVITY/ STATUS pin pairs which are used for SAS links for activity and status indicators. Each SAS link uses one ACTIVITY/STATUS pin pair. Note: The subsections that follow provide a brief overview of each feature. Refer to the appropriate chapter in the Intel® 81348 I/O Processor Developer’s Manual for full technical descriptions. 2.2.1 Host Interface The 81348 can be set up as either a single- or dual-function PCI device, providing PCI- X or PCI Express* interface or both PCI-X and PCI Express* interfaces. The PCI interface is selected as a reset option. When set up as a single-function PCI device, the Address Translation Unit (ATU) and the Messaging Unit (MU) provide the programming interface between the host processor and the 81348. When set up as a dual-function device, the ATU and the MU provide the programming interface between the host processor and the 81348 for function 0, whereas the Third-Party Messaging Interface (TPMI) provides the programming interface between the host processor and the 81348 for function 1. The PCI interface is selected as a reset option. • Address Translation Unit • DDR2 SDRAM Memory Controller • Messaging Unit • Transport DMA Controllers • Flash Interface Unit • UART Units • Chip Architecture Performance Unit • Address and Data Bus Parity Protection •I2C Bus Interface Units • Inter-Processor Communication • Multi-Port SRAM Memory Controller • Timers • Application DMA Controllers • Watchdog Timers • XSI System Controller (north and south) • Eight SAS Link Engines with integrated PHYs |
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