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EP1AGX35EF1152I6N Datasheet(PDF) 11 Page - Altera Corporation |
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EP1AGX35EF1152I6N Datasheet(HTML) 11 Page - Altera Corporation |
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11 / 234 page  Chapter 2: Arria GX Architecture 2–5 Transceivers © December 2009 Altera Corporation Arria GX Device Handbook, Volume 1 ■ Inter-transceiver block lines driven by reference clock input pins of other transceiver blocks 1 Altera® recommends using the dedicated reference clock input pins (REFCLK0 or REFCLK1 ) to provide reference clock for the transmitter PLL. Table 2–2 lists the adjustable parameters in the transmitter PLL. The transmitter PLL output feeds the central clock divider block and the local clock divider blocks. These clock divider blocks divide the high-speed serial clock to generate the low-speed parallel clock for the transceiver PCS logic and PLD-transceiver interface clock. Transmitter Phase Compensation FIFO Buffer A transmitter phase compensation FIFO is located at each transmitter channel’s logic array interface. It compensates for the phase difference between the transmitter PCS clock and the local PLD clock. The transmitter phase compensation FIFO is used in all supported functional modes. The transmitter phase compensation FIFO buffer is eight words deep in PCI Express (PIPE) mode and four words deep in all other modes. f For more information about architecture and clocking, refer to the Arria GX Transceiver Architecture chapter. Byte Serializer The byte serializer takes in two-byte wide data from the transmitter phase compensation FIFO buffer and serializes it into a one-byte wide data at twice the speed. The transmit data path after the byte serializer is 8 or 10 bits. This allows clocking the PLD-transceiver interface at half the speed when compared with the transmitter PCS logic. The byte serializer is bypassed in GIGE mode. After serialization, the byte serializer transmits the least significant byte (LSByte) first and the most significant byte (MSByte) last. Table 2–2. Transmitter PLL Specifications Parameter Specifications Input reference frequency range 50 MHz to 622.08 MHz Data rate support 600 Mbps to 3.125 Gbps Bandwidth Low, medium, or high |
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