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EP1AGX90CF780I6N Datasheet(PDF) 5 Page - Altera Corporation |
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EP1AGX90CF780I6N Datasheet(HTML) 5 Page - Altera Corporation |
5 / 234 page Chapter 1: Arria GX Device Family Overview 1–3 Features © December 2009 Altera Corporation Arria GX Device Handbook, Volume 1 Arria GX devices are available in space-saving FBGA packages (refer to Table 1–2). All Arria GX devices support vertical migration within the same package. With vertical migration support, designers can migrate to devices whose dedicated pins, configuration pins, and power pins are the same for a given package across device densities. For I/O pin migration across densities, the designer must cross-reference the available I/O pins with the device pin-outs for all planned densities of a given package type to identify which I/O pins are migratable. Source- synchronous transmit channels 29 29 29 29 29, 42 29 29 42 45 M512 RAM blocks (32 × 18 bits) 166 197 313 326 478 M4K RAM blocks (128 × 36 bits) 118 140 242 252 400 M-RAM blocks (4096 × 144 bits) 11 2 2 4 Total RAM bits 1,229,184 1,348,416 2,475,072 2,528,640 4,477,824 Embedded multipliers (18 × 18) 40 56 104 128 176 DSP blocks 10 14 26 32 44 PLLs 4 4 4 4, 8 4 8 8 Maximum user I/O pins 230, 341 230 341 229 350, 514 229 350 514 538 Table 1–1. Arria GX Device Features (Part 2 of 2) Feature EP1AGX20C EP1AGX35C/D EP1AGX50C/D EP1AGX60C/D/E EP1AGX90E C CDC D C D E E Table 1–2. Arria GX Package Options (Pin Counts and Transceiver Channels) (Part 1 of 2) Device Transceiver Channels Source-Synchronous Channels Maximum User I/O Pin Count Receive Transmit 484-Pin FBGA (23 mm) 780-Pin FBGA (29 mm) 1152-Pin FBGA (35 mm) EP1AGX20C 4 31 29 230 341 — EP1AGX35C 4 31 29 230 — — EP1AGX50C 4 31 29 229 — — EP1AGX60C 4 31 29 229 — — EP1AGX35D 8 31 29 — 341 — EP1AGX50D 8 31, 42 29, 42 — 350 514 |
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