M40SZ100Y, M40SZ100W

Operation

Doc ID 7528 Rev 3

9/24

2

Operation

The M40SZ100Y/W, as shown in Figure 5 on page 8, can control one (two, if placed in

parallel) standard low-power SRAM. This SRAM must be configured to have the chip enable

input disable all other input signals. Most slow, low-power SRAMs are configured like this,

however many fast SRAMs are not. During normal operating conditions, the conditioned

If chip enable access is in progress during a power fail detection, that memory cycle

continues to completion before the memory is write protected. If the memory cycle is not

A power failure during a WRITE cycle may corrupt data at the currently addressed location,

page 17).

independent of the E input, to allow for processor stabilization (see Figure 7 on page 11).

2.1

Data retention lifetime calculation

Most low power SRAMs on the market today can be used with the M40SZ100Y/W NVRAM

Controller. There are, however some criteria which should be used in making the final

choice of which SRAM to use. The SRAM must be designed in a way where the chip enable

input disables all other inputs to the SRAM. This allows inputs to the M40SZ100Y/W and

time must be sufficient to meet the system needs with the chip enable propagation delays

included.

If data retention lifetime is a critical parameter for the system, it is important to review the

data retention current specifications for the particular SRAMs being evaluated. Most SRAMs

specify a data retention current at 3.0 V. Manufacturers generally specify a typical condition

for room temperature along with a worst case condition (generally at elevated

temperatures). The system level requirements will determine the choice of which value to

the M40SZ100Y/W to determine the total current requirements for data retention. The

then be divided by this current to determine the amount of data retention available.