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EP1AGX50DF1152C6N Datasheet(PDF) 3 Page - Altera Corporation |
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EP1AGX50DF1152C6N Datasheet(HTML) 3 Page - Altera Corporation |
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3 / 234 page  © December 2009 Altera Corporation Arria GX Device Handbook, Volume 1 1. Arria GX Device Family Overview Introduction The Arria® GX family of devices combines 3.125 Gbps serial transceivers with reliable packaging technology and a proven logic array. Arria GX devices include 4 to 12 high-speed transceiver channels, each incorporating clock data recovery (CDR) technology and embedded SERDES circuitry designed to support PCI-Express, Gigabit Ethernet, SDI, SerialLite II, XAUI, and Serial RapidIO protocols, along with the ability to develop proprietary, serial-based IP using its Basic mode. The transceivers build upon the success of the Stratix® II GX family. The Arria GX FPGA technology offers a 1.2-V logic array with the right level of performance and dependability needed to support these mainstream protocols. Features The key features of Arria GX devices include: ■ Transceiver block features ■ High-speed serial transceiver channels with CDR support up to 3.125 Gbps. ■ Devices available with 4, 8, or 12 high-speed full-duplex serial transceiver channels ■ Support for the following CDR-based bus standards—PCI Express, Gigabit Ethernet, SDI, SerialLite II, XAUI, and Serial RapidIO, along with the ability to develop proprietary, serial-based IP using its Basic mode ■ Individual transmitter and receiver channel power-down capability for reduced power consumption during non-operation ■ 1.2- and 1.5-V pseudo current mode logic (PCML) support on transmitter output buffers ■ Receiver indicator for loss of signal (available only in PCI Express [PIPE] mode) ■ Hot socketing feature for hot plug-in or hot swap and power sequencing support without the use of external devices ■ Dedicated circuitry that is compliant with PIPE, XAUI, Gigabit Ethernet, Serial Digital Interface (SDI), and Serial RapidIO ■ 8B/10B encoder/decoder performs 8-bit to 10-bit encoding and 10-bit to 8-bit decoding ■ Phase compensation FIFO buffer performs clock domain translation between the transceiver block and the logic array ■ Channel aligner compliant with XAUI AGX51001-2.0 |
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