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EP1AGX35DF1152C6N Datasheet(PDF) 4 Page - Altera Corporation |
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EP1AGX35DF1152C6N Datasheet(HTML) 4 Page - Altera Corporation |
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4 / 234 page  1–2 Chapter 1: Arria GX Device Family Overview Features Arria GX Device Handbook, Volume 1 © December 2009 Altera Corporation ■ Main device features: ■ TriMatrix memory consisting of three RAM block sizes to implement true dual-port memory and first-in first-out (FIFO) buffers with performance up to 380 MHz ■ Up to 16 global clock networks with up to 32 regional clock networks per device ■ High-speed DSP blocks provide dedicated implementation of multipliers, multiply-accumulate functions, and finite impulse response (FIR) filters ■ Up to four enhanced phase-locked loops (PLLs) per device provide spread spectrum, programmable bandwidth, clock switch-over, and advanced multiplication and phase shifting ■ Support for numerous single-ended and differential I/O standards ■ High-speed source-synchronous differential I/O support on up to 47 channels ■ Support for source-synchronous bus standards, including SPI-4 Phase 2 (POS-PHY Level 4), SFI-4.1, XSBI, UTOPIA IV, NPSI, and CSIX-L1 ■ Support for high-speed external memory including DDR and DDR2 SDRAM, and SDR SDRAM ■ Support for multiple intellectual property megafunctions from Altera® MegaCore® functions and Altera Megafunction Partners Program (AMPPSM) ■ Support for remote configuration updates Table 1–1 lists Arria GX device features for FineLine BGA (FBGA) with flip chip packages. Table 1–1. Arria GX Device Features (Part 1 of 2) Feature EP1AGX20C EP1AGX35C/D EP1AGX50C/D EP1AGX60C/D/E EP1AGX90E C CDC D C D E E Package 484-pin, 780-pin (Flip chip) 484-pin (Flip chip) 780-pin (Flip chip) 484-pin (Flip chip) 780-pin, 1152-pin (Flip chip) 484-pin (Flip chip) 780-pin (Flip chip) 1152-pin (Flip chip) 1152-pin (Flip chip) ALMs 8,632 13,408 20,064 24,040 36,088 Equivalent logic elements (LEs) 21,580 33,520 50,160 60,100 90,220 Transceiver channels 4 4 848 4 8 12 12 Transceiver data rate 600 Mbps to 3.125 Gbps 600 Mbps to 3.125 Gbps 600 Mbps to 3.125 Gbps 600 Mbps to 3.125 Gbps 600 Mbps to 3.125 Gbps Source- synchronous receive channels 31 31 31 31 31, 42 31 31 42 47 |
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