Operation modes

M48T37Y, M48T37V

8/30

Doc ID 7019 Rev 9

2

Operation modes

As Figure 3 on page 7 shows, the static memory array and the quartz controlled clock

oscillator of the M48T37Y/V are integrated on one silicon chip. The memory locations that

provide user accessible BYTEWIDE™ clock information are in the bytes with addresses

7FF1 and 7FF9h-7FFFh (located in Table 5 on page 13). The clock locations contain the

century, year, month, date, day, hour, minute, and second in 24-hour BCD format.

Corrections for 28, 29 (leap year - valid until the year 2100), 30, and 31 day months are

made automatically.

Byte 7FF8h is the clock control register. This byte controls user access to the clock

information and also stores the clock calibration setting.

Byte 7FF7h contains the watchdog timer setting. The watchdog timer redirects an out-of-

control microprocessor and provides a reset or interrupt to it. Bytes 7FF2h-7FF5h are

reserved for clock alarm programming. These bytes can be used to set the alarm. This will

generate an active low signal on the IRQ/FT pin when the alarm bytes match the date,

hours, minutes, and seconds of the clock. The eight clock bytes are not the actual clock

counters themselves; they are memory locations consisting of BiPORT™ READ/WRITE

memory cells. The M48T37Y/V includes a clock control circuit which updates the clock bytes

with current information once per second. The information can be accessed by the user in

the same manner as any other location in the static memory array.

The M48T37Y/V also has its own power-fail detect circuit. The control circuitry constantly

tolerance, the circuit write protects the SRAM, providing a high degree of data security in the

maintains data and clock operation until valid power returns.

Table 2.

Operating modes

Note:

2.1

READ mode

The M48T37Y/V is in the READ mode whenever WRITE enable (W) is high and chip enable

(E) is low. The unique address specified by the 15 address inputs defines which one of the

32,752 bytes of data is to be accessed. Valid data will be available at the data I/O pins within

and output enable (G) access times are also satisfied. If the E and G access times are not

Mode

E

G

W

DQ0-DQ7

Power

Deselect

4.5 to 5.5 V

or

3.0 to 3.6 V

X

X

High Z

Standby

WRITE

Active

READ

Active

READ

High Z

Active

Deselect

(1)

1.

See Table on page 23 for details.

X

X

X

High Z

CMOS standby

Deselect

X

X

X

High Z

Battery backup mode