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313072-002 Datasheet(PDF) 6 Page - Intel Corporation |
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313072-002 Datasheet(HTML) 6 Page - Intel Corporation |
6 / 250 page 6 Intel® 6400/6402 Advanced Memory Buffer Datasheet 11.3.1 Fundamental Operations........................................................................ 113 11.3.2 Memory Addressing .............................................................................. 114 11.3.3 Memory Data Formatting ....................................................................... 123 11.3.4 Algorithmic Testing ............................................................................... 126 11.3.5 Error Reporting and Control ................................................................... 128 11.3.6 DRAM Throttling ................................................................................... 131 11.3.7 Refresh Control .................................................................................... 131 11.3.8 DRAM Initialization................................................................................ 132 11.4 MemBIST Memory Test Examples ...................................................................... 132 11.4.1 Write a Fixed Pattern to a Range of DRAM Addresses................................. 132 11.4.2 Write Random Data to a Range of DRAM Addresses and Check ................... 133 11.4.3 Write Leaping 0s to the Full DRAM Address Range and Check ..................... 134 11.4.4 Write 144-bit User-defined Pattern to a Range of Addresses and Check ........ 136 11.4.5 Test a Range of DRAM Addresses With March C- Algorithm ........................ 137 11.5 MemBIST Implementation................................................................................. 138 11.5.1 MemBIST Block Diagram ....................................................................... 138 11.5.2 MB Flow Control State Machine ............................................................... 139 11.5.3 CS Finite State Machine ......................................................................... 141 12 Ballout and Package Information ........................................................................... 143 12.1 Ballout .......................................................................................................... 143 12.2 655-Ball FBGA 0.8mm Pitch Pin Configuration...................................................... 143 12.3 Pin Assignments for the Advanced Memory Buffer (AMB)....................................... 144 12.4 Package Information ........................................................................................ 152 13 Signal Lists ............................................................................................................ 155 13.1 Conventions.................................................................................................... 155 13.2 Intel 6400/6402 Advanced Memory Buffer (AMB) Pin Description List...................... 156 14 Registers ............................................................................................................... 159 14.1 Access Mechanisms.......................................................................................... 159 14.1.1 Conflict Resolution and Usage Model Limitations ....................................... 159 14.1.2 FBD Data on Configuration Read Returns ................................................. 159 14.1.3 Non-Existent Register Bits...................................................................... 159 14.1.4 Register Attribute Definition ................................................................... 160 14.1.5 Binary Number Notation ........................................................................ 161 14.1.6 Function Mapping ................................................................................. 161 14.2 PCI Standard Header Identification Registers (Function 0) ..................................... 169 14.2.1 VID: Vendor Identification Register ......................................................... 169 14.2.2 DID: Device Identification Register.......................................................... 169 14.2.3 RID: Revision Identification Register ....................................................... 169 14.2.4 CCR: Class Code Register ...................................................................... 170 14.2.5 HDR: Header Type Register.................................................................... 170 14.3 FBD Link Registers (Function 1) ......................................................................... 170 14.3.1 FBD Link Control and Status................................................................... 170 14.3.2 SM Bus Register ................................................................................... 180 14.3.3 Error Registers ..................................................................................... 181 14.3.4 PERSONALITY BYTES Loaded From the SPD.............................................. 183 14.3.5 Hardware Configuration Registers ........................................................... 184 14.4 Implementation Specific FBD Registers (Function 2) ............................................. 185 14.5 DDR and Miscellaneous Registers (Function 3) ..................................................... 186 14.5.1 Memory Registers ................................................................................. 186 14.5.2 Memory BIST Registers ......................................................................... 191 14.5.3 Thermal Sensor Registers ...................................................................... 201 14.6 Implementation Specific DDR Initialization and Calibration Registers (Function 4) ...................................................................... 203 14.6.1 DDR Calibration.................................................................................... 203 14.6.2 Memory Interface Control ...................................................................... 219 |
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