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ICB2FL01G Datasheet(PDF) 8 Page - Infineon Technologies AG |
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ICB2FL01G Datasheet(HTML) 8 Page - Infineon Technologies AG |
8 / 56 page 2nd Generation FL-Controller for FL-Ballasts Datasheet Page 8 of 56 ICB2FL01G V1.2 A resistor, connected between ZCD winding and PIN 7, limits the sink and source current of the sense pin when the voltage of the ZCD winding exceeds the internal clamping levels (6.3V and -2.9V typically @ 5mA) of the IC. If the sensed voltage level of the ZCD winding is not sufficient (e.g. during start-up), an internal start-up timer will initiate a new cycle every 52µs after turn-off of the PFC Gate drive. The source current out of this pin during the on-time of the PFC-MOSFET indicates the voltage level of the AC supply voltage. During low input voltage levels the on-time of the PFC-MOSFET is enlarged in order to minimize gaps in the line current during zero crossing of the line voltage and improve the THD (Total Harmonic Distortion) of the line current. An optimization of the THD is possible by trimming of the resistor between this pin and the ZCD-winding. PFCVS (PFC voltage sense, Pin 8) The intermediate circuit voltage (bus voltage) at the smoothing capacitor is sensed by a resistive divider at this pin. The internal reference voltage for rated bus voltage is 2.5V. There are further thresholds at 0.3125V (12.5% of rated bus voltage) for the detection of open control loop and at 1.875V (75% of rated bus voltage) for the detection of an under voltage and at 2.725V (109% of rated bus voltage) for the detection of an overvoltage. The overvoltage threshold operates with a hysteresis of 100mV (4% of rated bus voltage). For the detection of a successful start-up the bus voltage is sensed at 95% (2.375V). It is recommended to use a small capacitor between this pin and GND as a spike suppression filter. In run mode, a PFC overvoltage stops the PFC Gate drive within 5µs. As soon as the bus voltage is less than 105% of rated level, the Gate drives are enabled again. If the overvoltage lasts for longer than 625ms, an inverter overvoltage is detected and turns off the inverter the gate drives also. This causes a power down and a power up when VBUS<109%. A bus under- (VBUS>75%) or inverter overvoltage during run mode is handled as fault U. In this situation the IC changes into power down mode and generates a delay of 100ms by an internal timer. Then start-up conditions are checked and if valid, a further start-up is initiated. If start-up conditions are not valid, a further delay of 100ms is generated. This procedure is repeated maximum seven times. If a start-up is successful within these seven cycles, the situation is interpreted as a short interruption of mains supply and the preheating is skipped. Any further start-up attempt is initiated including the preheating. RFRUN (Set R for run frequency, Pin 9) A resistor from this pin to ground sets the operating frequency of the inverter during run mode. Typical run frequency range is 20 kHz to 120 kHz. The set resistor R_RFRUN can be calculated based on the run frequency fRUN according to the equation: RUN FRUN f Hz R Ω ⋅ = 8 10 5 RFPH (Set R for preheat frequency, Pin 10) A resistor from this pin to ground sets together with the resistor at pin 9 the operating frequency of the inverter during preheat mode. Typical preheat frequency range is run frequency (as a minimum) to 150 kHz. The set resistor R_RFPH can be calculated based on the preheat frequency fPH and the resistor RRFRUN according to the equation: 1 10 5 8 − Ω ⋅ ⋅ = Hz R f R R RFRUN PH RFRUN RFPH RTPH (Set R for preheating time, Pin 11) A resistor from this pin to ground sets the preheating time of the inverter during preheat mode. A set resistor range from zero to 25kΩ corresponds to a range of preheating time from zero to 2500ms subdivided in 127 steps. Ω = k ms t R eHeating RTPH 100 Pr RES (Restart, Pin 12) A source current out of this pin via resistor and filament to ground monitors the existence of the low-side filament of the fluorescent lamp for restart after lamp removal. A capacitor from this pin directly to ground eliminates a superimposed AC voltage that is generated as a voltage drop across the low-side filament. With a second sense resistor the filament of a paralleled lamp can be included into the lamp removal sense. Note: during start up, the chip supply voltage Vcc has to be below 14.1V before VRES reaches the filament detection level. |
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