Operating modes

M48T512Y, M48T512V

10/23

Doc ID 5747 Rev 6

Table 4.

WRITE mode AC characteristics

2.3

Data retention mode

RAM. Should the supply voltage decay, the RAM will automatically deselect, write protecting

impedance and all inputs are treated as “Don't care.”

Note:

A power failure during a WRITE cycle may corrupt data at the current addressed location,

power to the internal battery, preserving data and powering the clock. The internal energy

source will maintain data in the M48T512Y/V for an accumulated period of at least 10 years

battery life.

Symbol

1.

M48T512Y

M48T512V

Unit

-70

-85

Min

Max

Min

Max

WRITE cycle time

70

85

ns

Address valid to WRITE enable low

0

0

ns

Address valid to chip enable low

0

0

ns

WRITE enable pulse width

50

60

ns

Chip enable low to chip enable high

55

65

ns

WRITE enable high to address transition

5

5

ns

Chip enable high to address transition

10

15

ns

Input valid to WRITE enable high

30

35

ns

Input valid to chip enable high

30

35

ns

WRITE enable high to input transition

5

5

ns

Chip enable high to input transition

10

15

ns

(2)(3)

2.

3.

If E goes low simultaneously with W going low, the outputs remain in the high impedance state.

WRITE enable low to output Hi-Z

25

30

ns

Address valid to write enable high

60

70

ns

Address valid to chip enable high

60

70

ns

(2)(3)

WRITE enable high to output transition

5

5

ns