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M48T129Y Datasheet(PDF) 7 Page - STMicroelectronics |
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M48T129Y Datasheet(HTML) 7 Page - STMicroelectronics |
7 / 28 page M48T129V, M48T129Y Operating modes Doc ID 5710 Rev 4 7/28 2 Operating modes Figure 3 on page 6 illustrates the static memory array and the quartz controlled clock oscillator. The clock locations contain the century, year, month, date, day, hour, minute, and second in 24-hour BCD format. Corrections for 28, 29 (leap year - valid until 2100), 30, and 31 day months are made automatically. The nine clock bytes (1FFFFh-1FFF9h and 1FFF1h) are not the actual clock counters, they are memory locations consisting of BiPORT™ READ/WRITE memory cells within the static RAM array. The M48T129Y/V includes a clock control circuit which updates the clock bytes with current information once per second. The information can be accessed by the user in the same manner as any other location in the static memory array. Byte 1FFF8h is the clock control register. This byte controls user access to the clock information and also stores the clock calibration setting. Byte 1FFF7h contains the watchdog timer setting. The watchdog timer can generate either a reset or an interrupt, depending on the state of the watchdog steering bit (WDS). Bytes 1FFF6h-1FFF2h include bits that, when programmed, provide for clock alarm functionality. Alarms are activated when the register content matches the month, date, hours, minutes, and seconds of the clock registers. Byte 1FFF1h contains century information. Byte 1FFF0h contains additional flag information pertaining to the watchdog timer, the alarm condition and the battery status. The M48T129Y/V also has its own power-fail detect circuit. This control circuitry constantly monitors the supply voltage for an out of tolerance condition. When VCC is out of tolerance, the circuit write protects the TIMEKEEPER ® register data and external SRAM, providing data security in the midst of unpredictable system operation. As VCC falls below battery backup switchover voltage (VSO), the control circuitry automatically switches to the battery, maintaining data and clock operation until valid power is restored. Table 2. Operating modes Note: X = VIH or VIL; VSO = battery backup switchover voltage. Mode VCC EG W DQ0- DQ7 Power Deselect 4.5 to 5.5V or 3.0 to 3.6V VIH X X High Z Standby WRITE VIL XVIL DIN Active READ VIL VIL VIH DOUT Active READ VIL VIH VIH High Z Active Deselect VSO to VPFD (min) (1) 1. See Table 12 on page 23 for details. X X X High Z CMOS standby Deselect ≤ VSO(1) X X X High Z Battery backup mode |
Similar Part No. - M48T129Y_10 |
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Similar Description - M48T129Y_10 |
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