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PIC24FJ128GA Datasheet(PDF) 11 Page - Microchip Technology

Part # PIC24FJ128GA
Description  64/80/100-Pin, 16-Bit General Purpose Flash Microcontrollers with Peripheral Pin Select
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

PIC24FJ128GA Datasheet(HTML) 11 Page - Microchip Technology

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 2008-2013 Microchip Technology Inc.
DS80368N-page 11
PIC24FJ256GA110 FAMILY
31. Module: Output Compare (Interrupt)
Under certain circumstances, an output com-
pare match may cause the interrupt flag (OCxIF)
to become set prior to the Change-of-State
(COS) of the OCx pin. This has been observed
when all of the following are true:
the
module
is
in
One-Shot
mode
(OCM<2:0> = 001, 010 or 100);
one of the timer modules is being used as
the time base; and
a timer prescaler other than 1:1 is selected.
If the module is re-initialized by clearing
OCM<2:0> after the One-Shot compare, the
OCx pin may not be driven as expected.
Work around
After OCxIF is set, allow an interval (in CPU
cycles) of at least twice the prescaler factor to
elapse before clearing OCM<2:0>. For example,
for a prescaler value of 1:8, allow 16 CPU cycles
to elapse after the interrupt.
Affected Silicon Revisions
32. Module: UART
When using UTXISEL<1:0> = 01 (interrupt when
last character is shifted out of the Transmit Shift
Register), and the final character is being shifted
out through the Transmit Shift Register, the TX
interrupt may occur before the final bit is shifted
out.
Work around
If it is critical that the interrupt processing occurs
only when all transmit operations are complete,
after which, the following work around can be
implemented:
Hold off the interrupt routine processing by adding
a loop at the beginning of the routine that polls the
Transmit Shift Register empty bit, as shown in
Example 2.
Affected Silicon Revisions
33. Module: Oscillator (Two-Speed Start-up)
Two-Speed Start-up is not functional. Leaving the
IESO Configuration bit in its default state
(Two-Speed Start-up enabled) may result in
unpredictable operation.
Work around
None. Always program the IESO Configuration bit
to disable this feature (CW2<15> = 0).
Affected Silicon Revisions
EXAMPLE 2:
DELAYING THE ISR BY POLLING THE TRMT BIT
A3
A5
A6
XX
X
A3
A5
A6
XX
X
A3
A5
A6
XX
X
// in UART2 initialization code
...
U2STAbits.UTXISEL0
= 1;
// Set to generate TX interrupt when all
U2STAbits.UTXISEL1
= 0;
// transmit operations are complete.
...
U2TXInterrupt(void)
{
while(U2STAbits.TRMT==0);
// wait for the transmit buffer to be empty
...
// process interrupt


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