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Product(s)

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Product(s)

All TIMING SPECIFICATIONS

Symbol

Parameter

Min.

Typ.

Max.

Unit

Frequency of master clocks

Depends on the device used and the

1.536

2.048

1.544

MHz

Width of Master Clock High

160

ns

Width of Master Clock Low

160

ns

Rise Time of Master Clock

50

ns

Fall Time of Master Clock

50

ns

Period of Bit Clock

485

488

15.725

ns

160

ns

160

ns

50

ns

50

ns

100

ns

Holding Time from Bit Clock Low to the Frame Sync

(long frame only)

0ns

Set-up Time from Frame Sync to Bit Clock (long frame only)

80

ns

Hold Time from 3rd Period of Bit Clock

Low to Frame Sync (long frame only)

100

ns

comes later and delay time from FSX to data output disabled

20

165

ns

(load = 150 pF plus 2 LSTTL loads)

0

150

ns

50

165

ns

50

ns

50

ns

Holding Time from Bit Clock High to Frame Sync (short frame only)

0

ns

(short frame sync pulse) - Note 1

80

ns

(short frame sync pulse) - Note 1

100

ns

140

ns

Minimum Width of the Frame Sync Pulse (low level)

(64 bit/s operating mode)

160

ns

Figure 1 : 64 k bits/s TIMING DIAGRAM. (see next page for complete timing)

ETC5064 - ETC5064-X - ETC5067 - ETC5067-X

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