TDA9884_06 datasheet(9/58 Pages) NXP

Part #	TDA9884

Description	I2C-bus controlled multistandard alignment-free IF-PLL for mobile reception

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Manufacturer	NXP [NXP Semiconductors]

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TDA9884_2

Product data sheet

Rev. 02 — 12 May 2006

9 of 58

Philips Semiconductors

TDA9884

I2C-bus controlled multistandard alignment-free IF-PLL

very long time constant for VIF gain increase is because the peak white level may appear

only once in a ﬁeld. In order to reduce this time constant, an additional level detector

increases the discharging current of the AGC capacitor (fast mode) in the event of a

decreasing VIF amplitude step controlled by the detected actual black level voltage. The

threshold level for fast mode AGC is typically

−6 dB video amplitude. The fast mode state

is also transferred to the SIF-AGC detector for speed-up. In case of missing peak white

pulses, the VIF gain increase is limited to typically +3 dB by comparing the detected

actual black level voltage with a corresponding reference voltage.

7.4 FPLL detector

The VIF ampliﬁer output signal is fed into a frequency detector and into a phase detector

via a limiting ampliﬁer for removing the video AM.

During acquisition the frequency detector produces a current proportional to the

frequency difference between the VIF and the VCO signals. After frequency lock-in the

phase detector produces a current proportional to the phase difference between the VIF

and the VCO signals. The currents from the frequency and phase detectors are charged

into the loop ﬁlter which controls the VIF VCO and locks it to the frequency and phase of

the VIF carrier.

For a positive modulated VIF signal, the charging currents are gated by the composite

sync in order to avoid signal distortion in case of overmodulation. The gating depth is

switchable via the I2C-bus.

7.5 VCO and divider

The VCO of the VIF-FPLL operates as an integrated low radiation relaxation oscillator at

double the picture carrier frequency. The control voltage, required to tune the VCO to

double the picture carrier frequency, is generated at the loop ﬁlter by the frequency phase

detector. The possible frequency range is 50 MHz to 140 MHz (typical value).

The oscillator frequency is divided-by-two to provide two differential square wave signals

with exactly 90 degrees phase difference, independent of the frequency, for use in the

FPLL detectors, the video demodulator and the intercarrier mixer.

7.6 AFC and digital acquisition help

Each relaxation oscillator of the VIF-PLL and FM-PLL demodulator has a wide frequency

range. To prevent false locking of the PLLs and with respect to the catching range, the

digital acquisition help provides an individual control, until the frequency of the VCO is

within the preselected standard dependent lock-in window of the PLL.

The in-window and out-window control at the FM-PLL is additionally used to mute the

audio stage (if auto mute is selected via the I2C-bus).

The working principle of the digital acquisition help is as follows. The PLL VCO output is

connected to a down counter which has a predeﬁned start value (standard dependent).

The VCO frequency clocks the down counter for a ﬁxed gate time. Thereafter, the down

counter stop value is analyzed. In case the stop value is higher (lower) than the expected

value range, the VCO frequency is lower (higher) than the wanted lock-in window

frequency range. A positive (negative) control current is injected into the PLL loop ﬁlter

and consequently the VCO frequency is increased (decreased) and a new counting cycle

starts.

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