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ISL59603IRZ-T7 Datasheet(PDF) 3 Page - Intersil Corporation |
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ISL59603IRZ-T7 Datasheet(HTML) 3 Page - Intersil Corporation |
3 / 27 page ISL59601, ISL59602, ISL59603, ISL59604, ISL59605 3 FN6739.1 November 23, 2010 Pin Descriptions PIN NUMBER PIN NAME DESCRIPTION INPUTS 3 IN+ High impedance analog input. This is the positive differential video input. Input signals are externally AC-coupled with an external 1.0μF capacitor. See Applications Information section for information regarding input network for Cat x and coax cables. 5 IN- High impedance analog input. This is the negative differential video input. Input signals are externally AC-coupled with an external 1.0μF capacitor. See Applications Information section for information regarding input network for Cat x and coax cables. 12 CFB Analog input. Bypass to ground with a 1500pF capacitor and connect to VIDEO OUT via a 0.022μF capacitor in series with a 300Ω resistor. OUTPUTS 13 VIDEO OUT Single-ended video output. The internal AGC sets this level to 2VP-P for a nominal 1VP-P (pre-cable) video source. DIGITAL I/O 7 EQ_DISABLE Digital Input. Equalizer Disable. 0: Normal Operation 1: Disables the equalizer to allow for insertion of upstream data onto the signal path, e.g. RS-485. 8 COLOR Digital I/O. Color Indicator/Override. 0: Monochrome 1: Color When used as an output, this pin indicates whether the incoming signal does or does not have a colorburst. When used as an input, this pin forces the state machine to into monochrome or color mode. See Figure 49 and associated text for more information on functionality. When COLOR is not externally driven, it is an output pin with a 13k (typical) output impedance. It is capable of driving 5V, high-impedance CMOS logic. Note: The COLOR indicator may be invalid for monochrome signals over greater than ~4800 feet. The device will still equalize properly if this occurs. 9 INVERT Digital I/O. Polarity Indicator/Override. 0: Nominal Polarity. 1: Inverted Polarity. When used as an output, this pin indicates the polarity of the incoming signal. When used as an input, this pin controls whether or not the input signal is inverted in the signal chain. See Figure 48 and associated text for more information on functionality. When INVERT is not externally driven, it is an output pin with a 13k (typical) output impedance. It is capable of driving 5V, high-impedance CMOS logic. In stand-alone mode, toggling this pin high-low-high or low-high-low will make the equalizer reacquire the signal. 10 LOCKED Digital Output. 0: Signal is not equalized (or not present). 1: Signal is equalized and settled. Note: The LOCKED indicator may be invalid for monochrome signals over greater than ~4800 feet. The device will still equalize properly if this occurs. 16 FREEZE Digital Input. Freezes equalizer in its current EQ state. 0: Continuous Update 1: Freeze EQ in current state. For stand-alone operations, connect FREEZE to the LOCKED pin to enter the recommended Lock Until Reset mode. SERIAL INTERFACE 18 SEN Digital Input. Serial Interface Enable. 19 SCK Digital Input. Serial Interface Clock Signal. 20 SD Digital I/O. Serial Interface Data Signal. |
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