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SAA7104E Datasheet(PDF) 9 Page - NXP Semiconductors |
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SAA7104E Datasheet(HTML) 9 Page - NXP Semiconductors |
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9 / 78 page  SAA7104E_SAA7105E_2 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 02 — 23 December 2005 9 of 78 Philips Semiconductors SAA7104E; SAA7105E Digital video encoder In order to display interlaced RGB signals through a euro-connector TV set, a separate digital composite sync signal (pin HSM_CSYNC) can be generated; it can be advanced up to 31 periods of the 27 MHz crystal clock in order to be adapted to the RGB processing of a TV set. The SAA7104E; SAA7105E synthesizes all necessary internal signals, color subcarrier frequency and synchronization signals from that clock. Wide screen signalling data can be loaded via the I2C-bus and is inserted into line 23 for standards using a 50 Hz field rate. VPS data for program dependent automatic start and stop of such featured VCRs is loadable via the I2C-bus. The IC also contains closed caption and extended data services encoding (line 21), and supports teletext insertion for the appropriate bit stream format at a 27 MHz clock rate (see Figure 15). It is also possible to load data for the copy generation management system into line 20 of every field (525/60 line counting). A number of possibilities are provided for setting different video parameters such as: • Black and blanking level control • Color subcarrier frequency • Variable burst amplitude etc. 7.1 Reset conditions To activate the reset a pulse at least of 2 crystal clocks duration is required. During reset (RESET = LOW) plus an extra 32 crystal clock periods, FSVGC, VSVGC, CBO, HSVGC and TTX_SRES are set to input mode and HSM_CSYNC and VSM are set to 3-state. A reset also forces the I2C-bus interface to abort any running bus transfer and sets it into receive condition. After reset, the state of the I/Os and other functions is defined by the strapping pins until an I2C-bus access redefines the corresponding registers; see Table 5. Table 5: Strapping pins Pin Tied Preset FSVGC LOW NTSC M encoding, PIXCLK fits to 640 × 480 graphics input HIGH PAL B/G encoding, PIXCLK fits to 640 × 480 graphics input VSVGC LOW 4:2:2 Y-CB-CR graphics input (format 0) HIGH 4:4:4 RGB graphics input (format 3) CBO LOW input demultiplex phase: LSB = LOW HIGH input demultiplex phase: LSB = HIGH HSVGC LOW input demultiplex phase: MSB = LOW HIGH input demultiplex phase: MSB = HIGH TTXRQ_XCLKO2 LOW slave (FSVGC, VSVGC and HSVGC are inputs, internal color bar is active) HIGH master (FSVGC, VSVGC and HSVGC are outputs) |
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