SCLK

FSYNC

DOUT

DIN

t

DOHD

t

FPW

t

SCLK

t

SF

t

SPW

t

SPW

t

FRAME

t

FPW

t

FS

t

DIHD

t

MSBPD

t

DIST

Bit15(MSB)

Bit14

Bit13

t

DOPD

CLK

t

CPW

t

CPW

t

CS

t

CLK

TIMING REQUIREMENTS: FRAME-SYNC FORMAT

ADS1174

ADS1178

TIMING CHARACTERISTICS: FRAME-SYNC FORMAT

SYMBOL

PARAMETER

MIN

TYP

MAX

UNIT

37

10,000

ns

CLK positive or negative pulse width

12

ns

Falling edge of CLK to falling edge of SCLK

–0.25

0.25

(1)

256

2560

FSYNC positive or negative pulse width

1

Rising edge of FSYNC to rising edge of SCLK

5

ns

Rising edge of SCLK to rising edge of FSYNC

5

ns

1

SCLK positive or negative pulse width

0.4

(3) (4)

SCLK falling edge to old DOUT invalid (hold time)

10

ns

(4)

SCLK falling edge to new DOUT valid (propagation delay)

31

ns

FSYNC rising edge to DOUT MSB valid (propagation delay)

31

ns

New DIN valid to falling edge of SCLK (setup time)

6

ns

(3)

Old DIN valid to falling edge of SCLK (hold time)

6

ns

(1)

(2)

(3)

ambient temperature). Under equal conditions, with DOUT connected directly to DIN, the timing margin is >4ns.

(4)

Load on DOUT = 20pF.

8

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