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IP3047CX6 Datasheet(PDF) 5 Page - NXP Semiconductors |
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IP3047CX6 Datasheet(HTML) 5 Page - NXP Semiconductors |
5 / 11 page IP3047CX6 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 2 — 23 November 2010 5 of 11 NXP Semiconductors IP3047CX6 Integrated dual channel passive LC-filter network with ESD protection 7. Application information The setup for measuring insertion loss in a 50 Ω system is shown in Figure 3. The insertion loss in a 50 Ω system for the two channels of the IP3047CX6 is shown in Figure 4. The insertion loss is measured directly on the wafer with coplanar probes. Unused pins are connected to ground with 50 Ω. Fig 3. Frequency response measurement configuration OUT 001aai755 50 Ω 50 Ω Vgen DUT IN TEST BOARD a. Channel 1 (pins A1 and A3). b. Channel 2 (pins B1 and B3). Fig 4. Measured insertion loss magnitudes 001aam535 −30 −20 −40 −10 0 s21 (dB) −50 f (MHz) 1104 103 10 102 001aam536 −30 −20 −40 −10 0 s21 (dB) −50 f (MHz) 1104 103 10 102 |
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