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MB90F598G Datasheet(PDF) 5 Page - Fujitsu Component Limited. |
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MB90F598G Datasheet(HTML) 5 Page - Fujitsu Component Limited. |
5 / 56 page MB90595G Series DS07-13705-7E 5 (Continued) *1: It is setting of DIP switch S2 when Emulation pod (MB2145-507) is used. Please refer to the MB2145-507 hardware manual (2.7 Emulator-specific Power Pin) about details. *2: Varies with conditions such as the operating frequency. (See “ ■ ELECTRICAL CARACTERISTICS.”) Features MB90598G MB90F598G MB90V595G CAN Interface Number of channels: 1 Conforms to CAN Specification Version 2.0 Part A and B Automatic re-transmission in case of error Automatic transmission responding to Remote Frame Prioritized 16 message buffers for data and ID’s Supports multiple messages Flexible configuration of acceptance filtering: Full bit compare / Full bit mask / Two partial bit masks Supports up to 1Mbps CAN bit timing setting: MB90598G/F598G:TSEG2 ≥ RSJW Stepping motor controller (4 channels) Four high current outputs for each channel Synchronized two 8-bit PWM’s for each channel External interrupt circuit Number of inputs: 8 Started by a rising edge, a falling edge, an “H” level input, or an “L” level input. Serial IO Clock synchronized transmission (31.25 K/62.5 K/125 K/500 K/1 Mbps at system clock frequency of 16 MHz) LSB first/MSB first Watchdog timer Reset generation interval: 3.58 ms, 14.33 ms, 57.23 ms, 458.75 ms (at oscillation of 4 MHz, minimum value) Flash Memory Supports automatic programming, Embedded Algorithm and Write/Erase/Erase-Suspend/Resume commands A flag indicating completion of the algorithm Hard-wired reset vector available in order to point to a fixed boot sector in Flash Memory Boot block configuration Erase can be performed on each block Block protection with external programming voltage Flash Writer from Minato Electronics, Inc. Low-power consumption (stand-by) mode Sleep/stop/CPU intermittent operation/watch timer/hardware stand-by Process CMOS Power supply voltage for operation*2 +5 V±10 % Package QFP-100 PGA-256 |
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