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MB90F443G Datasheet(PDF) 5 Page - Fujitsu Component Limited. |
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MB90F443G Datasheet(HTML) 5 Page - Fujitsu Component Limited. |
5 / 64 page MB90440G Series DS07-13716-3E 5 (Continued) *1 : Values with conditions such as the operating frequency (See section “ ELECTRICAL CHARACTERISTICS”) . *2 : DIP switch S2 when using emulation pad MB2145-507. The details are referred to hardware manual of MB2145-507. Part number MB90443G (under development) MB90F443G MB90V440G Parameter 16-bit Input Capture (8 channels) Rising edge, falling edge or rising & falling edge sensitive Four 16-bit capture registers Signals an interrupt upon external event 8/16-bit Programmable Pulse Generator (4 channels) Supports 8-bit and 16-bit operation modes Eight 8-bit reload counters Eight 8-bit reload registers for L pulse width Eight 8-bit reload registers for H pulse width A pair of 8-bit reload counters can be configured as one 16-bit reload counter or as 8-bit prescaler plus 8-bit reload counter 4 output pins Operation clock frequency. : fsys, fsys/21, fsys/22, fsys/23, fsys/24 or 128 µs@fosc = 4 MHz (fsys = System clock frequency, fosc = Oscillation clock frequency) CAN Interface 3 channels : Conforms to CAN Specification Version 2.0 Part A and B Automatic re-transmission in case of error Automatic transmission responding to Remote Frame Supports prioritized 16 message buffers for data and ID Flexible configuration of acceptance filtering : Full bit compare / Full bit mask / Two partial bit masks Supports up to 1 Mbps External Interrupt (8 channels) Can be programmed edge detection or level detection External bus interface The external access used selective 8-bit bus or 16-bit bus is available. (External bus mode) I/O Ports Virtually all external pins can be used as general purpose I/O All push-pull outputs and schmitt trigger inputs Bit-wise programmable as input/output or peripheral signal 32 kHz Subclock Sub-clock for low power operation Flash Memory Supports automatic programming, Embedded Algorithm Write/Erase/Erase-Suspend/Resume commands A flag indicating completion of the algorithm Number of erase cycles : 10,000 times Data retention time : 10 years Boot block configuration Erase can be performed on each block Block protection with external programming voltage |
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