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MB90F455S Datasheet(PDF) 5 Page - Fujitsu Component Limited. |
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MB90F455S Datasheet(HTML) 5 Page - Fujitsu Component Limited. |
5 / 80 page MB90455 Series DS07-13728-4E 5 (Continued) *1 : Settings of DIP switch S2 for using emulation pod MB2145-507. For details, See MB2145-507 Hardware Manual (2.7 Power Pin solely for Emulator). *2 : MB90F455S/F456S/F457S, MB90455S/456S/457S Part Number MB90F455 (S) / F456 (S) /F457 (S) MB90455 (S) / 456 (S) /457 (S) MB90V495G Parameter 8/16-bit PPG timer Number of channels: 2 (four 8-bit channels are available also) PPG operation is allowed with four 8-bit channels or one 16-bit channel. Outputting pulse wave of arbitrary cycle or arbitrary duty is allowed. Count clock: 62.5 ns to 1 µs (with 16 MHz machine clock) Delay interrupt generator module Interrupt generator module for task switching. Used for Real-time OS. DTP/External interrupt Number of inputs: 4 Activated by rising edge, falling edge, “H” level or “L” level input. External interrupt or expanded intelligent I/O service (EI2OS) is available. 8/10-bit A/D converter Number of channels: 8 Resolution: Selectable 10-bit or 8-bit. Conversion time: 6.125 µs (at 16-MHz machine clock, including sampling time) Sequential conversion of two or more successive channels is allowed. (Setting a maximum of 8 channels is allowed.) Single conversion mode : Selected channel is converted only once. Sequential conversion mode: Selected channel is converted repetitively. Halt conversion mode : Conversion of selected channel is stopped and activated alternately. UART 1 Number of channels: 1 Clock-synchronous transfer: 62.5 Kbps to 2 Mbps Clock-asynchronous transfer: 9,615 bps to 500 Kbps Communication is allowed by bi-directional serial communication function and master/slave type connection. |
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