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MAX16011TA-T Datasheet(PDF) 9 Page - Maxim Integrated Products |
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MAX16011TA-T Datasheet(HTML) 9 Page - Maxim Integrated Products |
9 / 12 page In normal operating mode, internal GATE1 output cir- cuitry enhances P1 to a 10V gate-to-source (VGS) for 11V < VCC < 72V. The constant 10V enhancement ensures P1 operates in a low RDS-ON mode, but the gate-source junction is not overstressed during high- battery-voltage application or transients (many MOSFET devices specify a ±20V VGS absolute maximum). As VCC drops below 10V GATE1 is limited to GND, reduc- ing P1 VGS to VCC - GND. In normal operation the P1 power dissipation is very low: P1 = ILOAD2 x RDS-ON During reverse-battery applications, GATE1 is limited to GND and the P1 gate-source junction is reverse biased. P1 is turned off and neither the MAX16013/ MAX16014 nor the load circuitry is exposed to the reverse-battery voltage. Care should be taken to place P1 (and its internal drain-to-source diode) in the correct orientation for proper reverse battery operation. P2 protects the load from input overvoltage conditions. During normal operating modes (the monitored voltage is below the adjusted overvoltage threshold), internal GATE2 output circuitry enhances P2 to a 10V gate-to- source (VGS) for 11V < VCC < 72V. The constant 10V enhancement ensures P2 operates in a low RDS-ON mode but the gate-to-source junction is not over- stressed during high-battery-voltage applications (many pFET devices specify a ±20V VGS absolute max- imum). As VCC drops below 10V, GATE2 is limited to GND, reducing P2 VGS to VCC - GND. In normal opera- tion, the P2 power dissipation is very low: P2 = ILOAD2 x RDS-ON During overvoltage conditions, P2 is either turned com- pletely off (overvoltage-switch mode) or cycled off-on- off (voltage-limiter mode). Care should be taken to place P2 (and its internal drain-to-source diode) in the correct orientation for proper overvoltage protection operation. During voltage-limiter mode, the drain of P2 is limited to the adjusted overvoltage threshold, while the battery (VCC) voltage rises. During prolonged over- voltage events, P2 temperature can increase rapidly due to the high power dissipation. The power dissipat- ed by P2 is: P2 = VDS-P2 x ILOAD = (VCC - VOV-ADJUSTED) x ILOAD where VCC ~ VBATTERY and VOV-ADJUSTED is the desired load limit voltage. For prolonged overvoltage events with high P2 power dissipation, proper heatsinking is required. Adding External Pullup Resistors It may be necessary to add an external resistor from VCC to GATE1 to provide enough additional pullup capability when the GATE1 input goes high. The GATE_ output can only source up to 1µA current. If the source current is less than 1µA, no external resistor may be necessary. However, to improve the pullup capability of the GATE_ output when it goes high, con- nect an external resistor between VCC and the GATE_. The application shows a 2M Ω resistor, which is large enough not to impact the sinking capability of the GATE_ (during normal operation) while providing enough pullup during an overvoltage event. With an 11V (worst case) VCC-to-gate clamp voltage and a sinking current of 75µA, the smallest resistor should be 11V/75µA, or about 147k Ω. However, since the GATE_ is typically low most of the time, a higher value should be used to reduce overall power consumption. Ultra-Small, Overvoltage Protection/ Detection Circuits _______________________________________________________________________________________ 9 |
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