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DS1556P-70+ Datasheet(PDF) 8 Page - Maxim Integrated Products

Part # DS1556P-70+
Description  1M, Nonvolatile, Y2K-Compliant Timekeeping RAM
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Manufacturer  MAXIM [Maxim Integrated Products]
Direct Link  https://www.maximintegrated.com/en.html
Logo MAXIM - Maxim Integrated Products

DS1556P-70+ Datasheet(HTML) 8 Page - Maxim Integrated Products

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DS1556 1M, Nonvolatile, Y2K-Compliant Timekeeping RAM
8 of 18
USING THE CLOCK ALARM
The alarm settings and control for the DS1556 reside within Registers 1FFF2h to 1FFF5h. Register
1FFF6h contains two alarm enable bits: Alarm Enable (AE) and Alarm in Backup Enable (ABE). The AE
and ABE bits must be set as described below for the
IRQ/FT output to be activated for a matched alarm
condition.
The alarm can be programmed to activate on a specific day of the month or repeat every day, hour,
minute, or second. It can also be programmed to go off while the DS1556 is in the battery-backed state of
operation to serve as a system wake-up. Alarm mask bits AM1 to AM4 control the alarm mode. Table 3
shows the possible settings. Configurations not listed in the table default to the once per second mode to
notify the user of an incorrect alarm setting.
Table 3. Alarm Mask Bits
AM4
AM3
AM2
AM1
ALARM RATE
1
1
1
1
Once per second
1
1
1
0
When seconds match
1
1
0
0
When minutes and seconds match
1
0
0
0
When hours, minutes, and seconds match
0
0
0
0
When date, hours, minutes, and seconds match
When the RTC Register values match Alarm Register settings, the Alarm Flag bit (AF) is set to a 1. If
Alarm Flag Enable (AE) is also set to a 1, the alarm condition activates the
IRQ/FT pin. The IRQ/FT
signal is cleared by a read or write to the Flags Register (Address 1FFF0h) as shown in Figure 2 and 3.
When
CE is active, the IRQ/FT signal may be cleared by having the address stable for as short as 15 ns
and either
OE or WE active, but is not guaranteed to be cleared unless t
RC is fulfilled. The alarm flag is
also cleared by a read or write to the Flags Register but the flag will not change states until the end of the
read/write cycle and the
IRQ/FT signal has been cleared.
Figure 2. Clearing
IRQ Waveforms
CE,
0V


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