Calculate the reset timeout period as follows:

accuracy and proper operation, minimize leakage at

Adjustable Delay (CDLY_)

250nA current source begins charging an external

capacitor connected from CDLY_ to GND. When the

voltage at CDLY_ reaches 1V, OUT_ goes high. When

OUT_ goes high, CDLY_ is immediately held low.

the equation:

nal propagation delay of the device. To ensure timing

accuracy and proper operation, minimize leakage

at CDLY.

Manual-Reset Input (

MR)

Many µP-based products require manual-reset capabil-

ity, allowing the operator, a test technician, or external

logic circuitry to initiate a reset. A logic-low on

MR

asserts

RESET low. RESET remains asserted while MR

is low and during the reset timeout period (140ms fixed

or capacitor adjustable) after

MR returns high. The MR

input has a 500nA internal pullup, so it can be left

unconnected, if not used.

MR can be driven with TTL or

CMOS logic levels, or with open-drain/collector outputs.

Connect a normally open momentary switch from

MR to

GND to create a manual-reset function. External

debounce circuitry is not required. If

MR is driven from

long cables or if the device is used in a noisy environ-

ment, connect a 0.1µF capacitor from

MR to GND to

provide additional noise immunity.

Pullup Resistor Values

The exact value of the pullup resistors for the open-

drain outputs is not critical, but some consideration

should be made to ensure the proper logic levels

when the device is sinking current. For example, if

sink current less than 0.5mA as shown in the

Electrical

Characteristics table. As a result, the pullup resistor

should be greater than 56kΩ. For a 12V pullup, the

resistor should be larger than 24kΩ. Note that the ability

Power-Supply Bypassing

as close to the device as possible to provide better

noise and transient immunity.

0V (MAX16026/MAX16028/MAX16030 Only)

sink current decreases. In order to ensure a valid out-

OUT/

RESET to GND.

Typical Application Circuits

Figures 4 and 5 show typical applications for the

MAX16025–MAX16030. In high-power applications,

using an n-channel device reduces the loss across the

MOSFETs as it offers a lower drain-to-source on-resis-

tance. However, an n-channel MOSFET requires a suffi-

The application in Figure 4 shows the MAX16027 con-

figured in a multiple-output sequencing application.

Figure 5 shows the MAX16029 in a power-supply

sequencing application using n-channel MOSFETs.

t

V

I

C

DELAY

TH CDLY

CH CDLY

CDLY

=×

+

×

−

−

−

35 10

6

t

V

I

C

RP

TH RESET

CH RESET

CRESET

=×

+

×

−

−

−

35 10

6

Dual-/Triple-/Quad-Voltage, Capacitor-

Adjustable, Sequencing/Supervisory Circuits

______________________________________________________________________________________

11