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DS21552 Datasheet(PDF) 5 Page - Maxim Integrated Products |
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DS21552 Datasheet(HTML) 5 Page - Maxim Integrated Products |
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5 / 137 page  DS21352/DS21552 5 of 137 1. LIST OF FIGURES Figure 3-1 SCT BLOCK DIAGRAM.........................................................................................................9 Figure 16-1 EXTERNAL ANALOG CONNECTIONS ..........................................................................87 Figure 16-2 OPTIONAL CRYSTAL CONNECTIONS ..........................................................................88 Figure 16-3 TRANSMIT WAVEFORM TEMPLANE............................................................................89 Figure 16-4 JITTER TOLERANCE.........................................................................................................91 Figure 16-5 JITTER ATTENUATION ....................................................................................................91 Figure 16-6 PROTECTED INTERFACE EXAMPLE FOR THE DS21552...........................................93 Figure 16-7 PROTECTED INTERFACE EXAMPLE FOR TE DS21352..............................................94 Figure 16-8 TYPICAL MONITOR PORT APPLICATION....................................................................95 Figure 19-1 JTAG FUNCTIONAL BLOCK DIAGRAM......................................................................100 Figure 19-2 TAP CONTROLLER STATE DIAGRAM ........................................................................103 Figure 20-1 IBO BASIC CONFIGURATION USING 4 SCTS ............................................................110 Figure 21-1 RECEIVE SIDE D4 TIMING.............................................................................................111 Figure 21-2 RECEIVE SIDE ESF TIMING...........................................................................................112 Figure 21-3 RECEIVE SIDE BOUNDARY TIMING (with elastic store disabled)..............................113 Figure 21-4 RECEIVE SIDE 1.544 MHz BOUNDARY TIMING (with elastic store enabled) ...........113 Figure 21-5 RECEIVE SIDE 2.048 MHz BOUNDARY TIMING (with elastic store enabled) ...........114 Figure 21-6 RECEIVE SIDE INTERLEAVE BUS OPERATION, BYTE MODE ..............................115 Figure 21-7 RECEIVE SIDE INTERLEAVE BUS OPERATION, FRAME MODE...........................116 Figure 21-8 TRANSMIT SIDE D4 TIMING.........................................................................................117 Figure 21-9 TRANSMIT SIDE ESF TIMING.......................................................................................118 Figure 21-10 TRANSMIT SIDE BOUNDARY TIMING (with elastic store disabled) ........................119 Figure 21-11 TRANSMIT SIDE 1.544 MHz BOUNDARY TIMING (with elastic store enabled)......119 Figure 21-12 TRANSMIT SIDE 2.048 MHz BOUNDARY TIMING (with elastic store enabled)......120 Figure 21-13 TRANSMIT SIDE INTERLEAVE BUS OPERATION, BYTE MODE.........................121 Figure 21-14 TRANSMIT SIDE INTERLEAVE BUS OPERATION, FRAME MODE .....................122 Figure 22-1 RECEIVE DATA FLOW ...................................................................................................123 Figure 22-2 TRANSMIT DATA FLOW................................................................................................124 Figure 24-1 INTEL BUS READ TIMING (BTS=0 / MUX=1) .............................................................127 Figure 24-2 INTEL BUS WRITE TIMING (BTS=0 / MUX=1) ...........................................................127 Figure 24-3 MOTOROLA BUS TIMING (BTS=1 / MUX=1)..............................................................128 Figure 24-4 INTEL BUS READ TIMING (BTS=0 / MUX=0) ..............................................................130 Figure 24-5 INTEL BUS READ TIMING (BTS=0 / MUX=0) .............................................................130 Figure 24-6 MOTOROLA BUS READ TIMING (BTS=1 / MUX=0)..................................................131 Figure 24-7 MOTOROLA BUS READ TIMING (BTS=1 / MUX=0)..................................................131 Figure 24-8 RECEIVE SIDE TIMING ..................................................................................................133 Figure 24-9 RECEIVE SIDE TIMING, ELASTIC STORE ENABLED...............................................134 Figure 24-10 RECEIVE LINE INTERFACE TIMING .........................................................................135 Figure 24-11 TRANSMIT SIDE TIMING.............................................................................................137 Figure 24-12 TRANSMIT SIDE TIMING, ELASTIC STORE ENABLED .........................................138 Figure 24-13 TRANSMIT LINE INTERFACE TIMING......................................................................138 |
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