HEF4094BT datasheet(8/19 Pages) NXP

Part #	HEF4094BT

Description	8-stage shift-and-store register

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HEF4094B_8

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Product data sheet

Rev. 08 — 2 April 2010

8 of 19

NXP Semiconductors

HEF4094B

8-stage shift-and-store register

[1]

The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (CL in pF).

tPLZ

LOW to OFF-state

propagation delay

OE to QPn;

see Figure 8

5 V

-

80

160

ns

10 V

-

40

80

ns

15 V

-

30

60

ns

tsu

set-up time

D to CP;

see Figure 9

5 V

60

30

-

ns

10 V

20

10

-

ns

15 V

15

5

-

ns

th

hold time

D to CP;

see Figure 9

5 V

+5

−15

-

ns

10 V

20

5

-

ns

15 V

20

5

-

ns

tW

pulse width

minimum LOW

clock pulse;

see Figure 6

5 V

60

30

-

ns

10 V

30

15

-

ns

15 V

24

12

-

ns

minimum HIGH

strobe pulse;

see Figure 7

5 V

40

20

-

ns

10 V

30

15

-

ns

15 V

24

12

-

ns

fmax

maximum frequency

see Figure 6

5 V

5

10

-

MHz

10 V

11

22

-

MHz

15 V

14

28

-

MHz

Table 7.

Dynamic characteristics …continued

VSS = 0 V; Tamb = 25 °C; for test circuit see Figure 10; unless otherwise specified.

Symbol

Parameter

Conditions

VDD

Extrapolation formula

Min

Typ

Max

Unit

Table 8.

Dynamic power dissipation

VSS = 0 V; tr = tf ≤ 20 ns; Tamb = 25 °C.

Symbol

Parameter

VDD

Typical formula for PD (μW)

where:

PD

dynamic power

dissipation

5 V

PD = 2100 × fi + Σ(fo × CL) × VDD2

fi = input frequency in MHz,

fo = output frequency in MHz,

CL = output load capacitance in pF,

VDD = supply voltage in V,

Σ(f

o × CL) = sum of the outputs.

10 V

PD = 9700 × fi + Σ(fo × CL) × VDD2

15 V

PD = 26000 × fi + Σ(fo × CL) × VDD2

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