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ISP1504C1 Datasheet(PDF) 9 Page - NXP Semiconductors

Part # ISP1504C1
Description  ULPI Hi-Speed Universal Serial Bus On-The-Go transceiver
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

ISP1504C1 Datasheet(HTML) 9 Page - NXP Semiconductors

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ISP1504A1_ISP1504C1_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 6 August 2007
8 of 80
NXP Semiconductors
ISP1504A1; ISP1504C1
ULPI HS USB OTG transceiver
Differential and single-ended receivers to receive data at high-speed, full-speed and
low-speed
Squelch circuit to detect high-speed bus activity
High-speed disconnect detector
45
Ω high-speed bus terminations on DP and DM
1.5 k
Ω pull-up resistor on DP
15 k
Ω pull-down resistor on DP and DM
For details on controlling resistor settings, see Table 8.
7.4 Voltage regulator
The ISP1504x1 contains a built-in voltage regulator that conditions the VCC supply for use
inside the ISP1504x1. The voltage regulator:
Supports input supply range of 3.0 V < VCC < 4.5 V
Can be supplied from a battery with a voltage range of 3.0 V to 4.5 V
Supplies internal circuitry with 1.8 V and 3.3 V
Automatically bypasses the internal 3.3 V regulator when VCC < 3.5 V, drawing power
directly from the VCC pin
To save current, the voltage regulator will be shut down, if VCC(I/O) is not present or if
pin CS_N/PWRDN is at a HIGH level.
Remark: The REG1V8 and REG3V3 pins require an external 0.1
µF capacitor in parallel
with a 4.7
µF capacitor. For details, see Section 15.
7.5 Crystal oscillator and PLL
The ISP1504x1 has a built-in crystal oscillator and a Phase-Locked Loop (PLL) for clock
generation.
The crystal oscillator takes a sine-wave input from an external crystal, on the XTAL1 pin,
and converts it to a square wave clock for internal use. Alternatively, a square wave clock
of the same frequency can also be directly driven into the XTAL1 pin. Using an existing
square wave clock can save the cost of the crystal and also reduce the board size. The
input clock or crystal frequency supported is 19.2 MHz or 26 MHz.
The PLL produces the following frequencies, irrespective of the clock source:
60 MHz clock for the ULPI interface controller
1.5 MHz for the low-speed USB data
12 MHz for the full-speed USB data
480 MHz for the high-speed USB data
Other internal frequencies for data conversion and data recovery
7.6 OTG module
This module contains several sub-blocks that provide all the functionality required by the
USB OTG specification. Specifically, it provides the following circuits:


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