 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
DS90LV028AQMA Datasheet(PDF) 4 Page - National Semiconductor (TI) |
|
|
||||||||||||||||||||||||||||||
DS90LV028AQMA Datasheet(HTML) 4 Page - National Semiconductor (TI) |
|
|
4 / 10 page  Applications Information General application guidelines and hints for LVDS drivers and receivers may be found in the following application notes: LVDS Owner's Manual (lit #550062-003), AN-808, AN-977, AN-971, AN-916, AN-805, AN-903. LVDS drivers and receivers are intended to be primarily used in an uncomplicated point-to-point configuration as is shown in Figure 3. This configuration provides a clean signaling en- vironment for the fast edge rates of the drivers. The receiver is connected to the driver through a balanced media which may be a standard twisted pair cable, a parallel pair cable, or simply PCB traces. Typically the characteristic impedance of the media is in the range of 100 Ω. A termination resistor of 100 Ω should be selected to match the media, and is located as close to the receiver input pins as possible. The termination resistor converts the driver output (current mode) into a volt- age that is detected by the receiver. Other configurations are possible such as a multi-receiver configuration, but the effects of a mid-stream connector(s), cable stub(s), and other impedance discontinuities as well as ground shifting, noise margin limits, and total termination loading must be taken into account. The DS90LV028AQ differential line receiver is capable of de- tecting signals as low as 100 mV, over a ±1V common-mode range centered around +1.2V. This is related to the driver off- set voltage which is typically +1.2V. The driven signal is centered around this voltage and may shift ±1V around this center point. The ±1V shifting may be the result of a ground potential difference between the driver's ground reference and the receiver's ground reference, the common-mode ef- fects of coupled noise, or a combination of the two. The AC parameters of both receiver input pins are optimized for a recommended operating input voltage range of 0V to +2.4V (measured from each pin to ground). The device will operate for receiver input voltages up to V CC, but exceeding VCC will turn on the ESD protection circuitry which will clamp the bus voltages. POWER DECOUPLING RECOMMENDATIONS Bypass capacitors must be used on power pins. Use high fre- quency ceramic (surface mount is recommended) 0.1 μF and 0.01 μF capacitors in parallel at the power supply pin with the smallest value capacitor closest to the device supply pin. Ad- ditional scattered capacitors over the printed circuit board will improve decoupling. Multiple vias should be used to connect the decoupling capacitors to the power planes. A 10 μF (35V) or greater solid tantalum capacitor should be connected at the power entry point on the printed circuit board between the supply and ground. PC BOARD CONSIDERATIONS Use at least 4 PCB board layers (top to bottom): LVDS sig- nals, ground, power, TTL signals. Isolate TTL signals from LVDS signals, otherwise the TTL signals may couple onto the LVDS lines. It is best to put TTL and LVDS signals on different layers which are isolated by a power/ground plane(s). Keep drivers and receivers as close to the (LVDS port side) connectors as possible. DIFFERENTIAL TRACES Use controlled impedance traces which match the differential impedance of your transmission medium (ie. cable) and ter- mination resistor. Run the differential pair trace lines as close together as possible as soon as they leave the IC (stubs should be < 10mm long). This will help eliminate reflections and ensure noise is coupled as common-mode. In fact, we have seen that differential signals which are 1mm apart radi- ate far less noise than traces 3mm apart since magnetic field cancellation is much better with the closer traces. In addition, noise induced on the differential lines is much more likely to appear as common-mode which is rejected by the receiver. Match electrical lengths between traces to reduce skew. Skew between the signals of a pair means a phase difference between signals which destroys the magnetic field cancella- tion benefits of differential signals and EMI will result! (Note that the velocity of propagation, v = c/E r where c (the speed of light) = 0.2997mm/ps or 0.0118 in/ps). Do not rely solely on the autoroute function for differential traces. Carefully review dimensions to match differential impedance and provide iso- lation for the differential lines. Minimize the number of vias and other discontinuities on the line. Avoid 90° turns (these cause impedance discontinuities). Use arcs or 45° bevels. Within a pair of traces, the distance between the two traces should be minimized to maintain common-mode rejection of the receivers. On the printed circuit board, this distance should remain constant to avoid discontinuities in differential impedance. Minor violations at connection points are allow- able. TERMINATION Use a termination resistor which best matches the differential impedance or your transmission line. The resistor should be between 90 Ω and 130Ω. Remember that the current mode outputs need the termination resistor to generate the differ- ential voltage. LVDS will not work correctly without resistor termination. Typically, connecting a single resistor across the pair at the receiver end will suffice. Surface mount 1% - 2% resistors are the best. PCB stubs, component lead, and the distance from the termination to the receiver inputs should be minimized. The distance between the termination resistor and the receiver should be < 10mm (12mm MAX). INPUT FAILSAFE BIASING External pull up and pull down resistors may be used to pro- vide enough of an offset to enable an input failsafe under open-circuit conditions. This configuration ties the positive LVDS input pin to VDD thru a pull up resistor and the negative LVDS input pin is tied to GND by a pull down resistor. The pull up and pull down resistors should be in the 5k Ω to 15kΩ range to minimize loading and waveform distortion to the driver. The common-mode bias point ideally should be set to approxi- mately 1.2V (less than 1.75V) to be compatible with the internal circuitry. Please refer to application note AN-1194, “Failsafe Biasing of LVDS Interfaces” for more information. PROBING LVDS TRANSMISSION LINES Always use high impedance (> 100k Ω), low capacitance (< 2 pF) scope probes with a wide bandwidth (1 GHz) scope. Improper probing will give deceiving results. CABLES AND CONNECTORS, GENERAL COMMENTS When choosing cable and connectors for LVDS it is important to remember: Use controlled impedance media. The cables and connectors you use should have a matched differential impedance of about 100 Ω. They should not introduce major impedance dis- continuities. Balanced cables (e.g. twisted pair) are usually better than unbalanced cables (ribbon cable, simple coax) for noise re- www.national.com 4 |
Similar Part No. - DS90LV028AQMA |
|
Similar Description - DS90LV028AQMA |
|
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.COM |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
